Writing a #LUA interpreter in verilog on an #FPGA is of interest to me. But sadly the newest vrsions of LUA are based on a register virtual machine, only the older versions are based ona. stack virtual machine.
I did think about the sexual harassment issue, but it only applies to part of the Union target market. The other issues apply to everyone. It could be added as harassment, and discrimination. That covers a lot of cases.. So I edited it.
Union organising for software professionals is a great target market for the #Fediverse. Here are some of the issues.
1. Remote work or paid commuting. 2. Anonymity for union organisers. 3. Ergonimic workstations, not laptops. 4. (Australian) Right to disconnect. 5. No H1Bs, they cannot strike. 6. No AI. It is designed to lower our wages. Besides it does not work, wastes our time and is bad for the climate.
Given the number of people interested in the book "Delay, Deny, Defend" by Jay Feinman, the normal capitalist thing would be for the publisher to issue a new print run.
I am dropping the idea of a LISP soft core. I am focussing on tiny #Forth interpreters on #RISCV. The problem with LISP is that it is not very readable, say compared to Python, and mapping car/crd to vectors is memory inefficient. And not that much demand.
#Forth has a lot to offer the soft core community.
Since we are reaching the end of Moore's law, there is now an opportunity for language specific processors. Already there are soft core #Lisp, #Pascal, and #Forth processors.
A group of Boeing employees are sitting on a plane getting ready for takeoff. The pilot comes on over the intercom and says "Folks, we're pleased to have you flying with us on our brand new 737, fresh from our good friends at Boeing!"
Immediately, the Boeing employees all scramble to get out of their seats and off the plane as quickly as possible. It's utter pandemonium in the aisles as everyone starts to panic.
@fediforum I do not have any bee keeper friends either. I chose bee keepers as an example of a social group that might love to get together and talk about what their issues are. I think they are interested in urban beekeeping, colony die off and other issues.
I am building tiny real-time #Forth co-processors for MicroPython, Circuit Python and RISC-V. On FPGA's a stack machine can be 1/2 the size of a 32 bit RISC-V soft core.#Forth, #MicroPython #CircuitPython #Riscv #StackMachine #FPGA #Verilog #realtime