Conversation

Notices

1. Embed this notice
   Alfred M. Szmidt (amszmidt@mastodon.social)'s status on Tuesday, 05-Nov-2024 16:31:28 JST Alfred M. Szmidt

   Calling all #HDL hackers! I need help in putting the #MIT #CADR onto a FPGA board. #VHDL, #Verilog, does not matter much. Who is up for a fun challange? #LispMachine

   • Embed this notice
     Forth Computer (pythonlinks@mastodon.social)'s status on Tuesday, 05-Nov-2024 16:31:28 JST Forth Computer

     in reply to

     @amszmidt This sounds very interesting.

     My expertise is languages on stack machines. One of the lisp patents included garbage collection in hardware.

     I am now searching for articles on the cadr architecture.

   • Embed this notice
     Alfred M. Szmidt (amszmidt@mastodon.social)'s status on Tuesday, 05-Nov-2024 16:35:14 JST Alfred M. Szmidt

     in reply to

     • Forth Computer

     @PythonLinks You can probably find everything there is to know about the CADR at https://tumbleweed.nu/lm-3 :-) https://tumbleweed.nu/r/lm-3/uv/cadr.html https://tumbleweed.nu/lm-3/schematics.html

   • Embed this notice
     Alfred M. Szmidt (amszmidt@mastodon.social)'s status on Tuesday, 05-Nov-2024 16:58:13 JST Alfred M. Szmidt

     in reply to

     • Forth Computer

     @PythonLinks Fun. Plus, I want a "real" CADR that isn't simulated in C. 😃 I've been restoring the software for it for many many years and it is a fun little system to hack on, having a "real" and dedicated machine would be really fun.

   • Embed this notice
     Forth Computer (pythonlinks@mastodon.social)'s status on Tuesday, 05-Nov-2024 16:58:14 JST Forth Computer

     in reply to

     @amszmidt
     Here is a good description of the cpu architecture.
     https://metebalci.com/blog/cadr-lisp-machine-and-cadr-processor/#system-overview

     32 bit code but 42 bit microcode. Brilliant Allows for VLIW parallel microcode.

     Thsoe guys were very smart.

   • Embed this notice
     Forth Computer (pythonlinks@mastodon.social)'s status on Tuesday, 05-Nov-2024 16:58:14 JST Forth Computer

     in reply to

     @amszmidt
     It will take a couple of readings to really understand it.

     Why do you want to build this?

   • Embed this notice
     Alfred M. Szmidt (amszmidt@mastodon.social)'s status on Tuesday, 05-Nov-2024 17:34:47 JST Alfred M. Szmidt

     in reply to

     • Forth Computer

     @PythonLinks Here is Knights thesis (https://tumbleweed.nu/r/lm-3/uv/knight-thesis.html); I'm still converting to something nice. And at some point will add the figures too. Might be interesting for you.

   • Embed this notice
     Forth Computer (pythonlinks@mastodon.social)'s status on Wednesday, 06-Nov-2024 03:55:43 JST Forth Computer

     in reply to

     Since we are reaching the end of Moore's law, there is now an opportunity for language specific processors. Already there are soft core #Lisp, #Pascal, and #Forth processors.

     The MIT #CADR Machine is most interesting.

     https://tumbleweed.nu/r/lm-3/uv/knight-thesis.html#Typed-Data

     @amszmidt

   • Embed this notice
     Forth Computer (pythonlinks@mastodon.social)'s status on Wednesday, 06-Nov-2024 05:16:55 JST Forth Computer

     in reply to

     Can you tell me more about the A and M memories of the original LISP machines? How are they used.

     On a modern FPGA, pico-ice board you can get > 1 Mbit on board memory for $35.

     @amszmidt

   • Embed this notice
     Forth Computer (pythonlinks@mastodon.social)'s status on Wednesday, 06-Nov-2024 05:23:40 JST Forth Computer

     in reply to

     I could not download the Henry Barker 1977 Garbage Collection paper.

     Real time #garbage #collection of the LISP machines was a killer app feature, now mostly disappeared commercially.

     Can you recommend a good link to read more.
     @amszmidt

   • Embed this notice
     Alfred M. Szmidt (amszmidt@mastodon.social)'s status on Wednesday, 06-Nov-2024 05:24:29 JST Alfred M. Szmidt

     in reply to

     • Forth Computer

     @PythonLinks AMEM is a 1kx32 bit memory that is partially mirrored in MMEM which is 32x32. They are used more or less as registers, where each address has some purpose. https://tumbleweed.nu/r/sys/file?ci=tip&name=ucadr/uc-parameters.lisp.230&ln=373-557 and https://tumbleweed.nu/r/sys/file?ci=tip&name=ucadr/uc-parameters.lisp.230&ln=559-1269 might give you an idea.

   • Embed this notice
     Alfred M. Szmidt (amszmidt@mastodon.social)'s status on Wednesday, 06-Nov-2024 18:18:46 JST Alfred M. Szmidt

     in reply to

     • Forth Computer

     @PythonLinks You mean this paper?
     https://dspace.mit.edu/bitstream/handle/1721.1/41969/AI_WP_149.pdf

     The Lisp Machine did not have RT GC. It was stop-and-copy for most part of its life.

   • Embed this notice
     Alfred M. Szmidt (amszmidt@mastodon.social)'s status on Wednesday, 06-Nov-2024 18:24:01 JST Alfred M. Szmidt

     in reply to

     • Forth Computer

     @PythonLinks Barkers paper describes an incremental one, which is not the same as a real-time one. Most, if not all systems today use something similar. RT GC does also not make much sense, there are better ways to do GC than that ...

   • Embed this notice
     Forth Computer (pythonlinks@mastodon.social)'s status on Friday, 08-Nov-2024 19:16:54 JST Forth Computer

     in reply to

     I am dropping the idea of a LISP soft core. I am focussing on tiny #Forth interpreters on #RISCV. The problem with LISP is that it is not very readable, say compared to Python, and mapping car/crd to vectors is memory inefficient. And not that much demand.

     #Forth has a lot to offer the soft core community.

     @amszmidt

   • Embed this notice
     Alfred M. Szmidt (amszmidt@mastodon.social)'s status on Friday, 08-Nov-2024 21:47:44 JST Alfred M. Szmidt

     in reply to

     • Forth Computer

     @PythonLinks There are plenty of soft cores for Forth. You can do one in half a screen of VHDL. I do not know why you'd map CAR/CDR to vectors ... Lisp supports strings just as any language.

     As for Python being readable .. we will have to disagree on that.