Notices by Studio 8502 :verified: (mos_8502@soc.studio8502.ca), page 2

VERA outputs 12-bit R4G4B4 video, which gets passed through a trio of 4-bit R2R ladder DACs before hitting the 15-pin video connector. The diodes are for ESD protection.

The SD card is handled using the VERA's SPI bus, which it uses to bootload the FPGA as well; once the FPGA is loaded, the CDONE output goes high, which causes the bus switch here to connect the SD card port to the pins. Select logic is multiplexed in the glue chip, so the FPGA's select line selects the SD card if and only if CDONE is high.

We have two SNES controller ports which have been enhanced by assigning the unused two pins to the I2C bus; this will enable many accessories to be made for this port, including keyboards or other such custom interface devices.

The system supports four SNES controllers; the signals for all four are on the internal control header, suitable for whatever case design you have in mind.

The clock port does pretty much what the Amiga's clock port does, plus a debug serial line and I2C.

The power supply is stupid simple. USB-C provides 5V/3A (15W) of DC, which feeds a 3.3V regulator. The reset supervisor only allows /RES to go high when the power stabilizes, and also debounces the reset button.

Finally, the cartridge/expansion port. Not a multi-slot bus, just a single port for a cartridge which is mechanically and electrically compatible with the Mega Drive/Genesis, but not logically so. This makes producing physical releases very easy. The cart slot provides the full system bus, DMA access, I2C, and audio passthrough for whatever crazy shit you can come up with.

Aside from some buttons and LEDs, that's your lot. I hope it works. If you notice something I have got wrong, you would be doing me a favour telling me about it. I intend this design to be as inexpensive to manufacture as possible; Rev0 is specifically to prove it works, while Rev1 will fix any known issues in Rev0, and make the CPU a TQFP-100 instead of the PLCC-84.

This design represents the sum total of everything I want in a retro computer/games machine. It will be simple to program for (in C or asm, hopefully also Pascal and other languages eventually) *and* on (once it has native on-device tooling). It has the hardware muscle to do almost anything with sprites and tiles you can come up with. It is superior hardware to the SNES -- much closer to the Neo•Geo, though not its equal. Faster than an unaccelerated Apple IIgs or Amiga 1200, as well.

It is also what I consider the minimum viable product. I have removed everything I could justify calling bloat, pared down the hardware as far as I can do, made it into something that can be produced at either major hobbyist fab house from all new parts, all still in production.

The design will be released under the CERN Open Hardware Licence (Permissive) version 2. I don't care who makes them, who sells them, how much they charge, none of that means anything to me. I plan to make and sell them as inexpensively as possible, because if people can't afford your fancy tech toy, then it doesn't matter how good it is, it still sucks.

CUPL is a terrible HDL, but it's what the cheap 22LV10C uses.

If someone has a toolchain I can use to turn Verilog into something I can burn into a 22LV10C with a Minipro type ROM programmer, I would love to know.

See now that I don't hate.

$20USD via PayPal to the first person who is already following me, who comes up with a logo for the Sentinel 65X that I think is cool enough to use.

Condition: The copyright of the winner of the prize gets transferred to me, so I can put restrictions on its use.

What I want: A logo that is identifiable, public-acceptable (See AROS for an idea of what not to do) that screams "cool new retrocomputer", and that is not too close to anything out there now. Other than that, go wild.

Oh, you're into electronics? Calculate the resistance of this part, then.

Okay. You can either have your decentralized social media that anyone can run, or you can have your walled garden where the corpos aren’t allowed to try to hang with the cool kids. You can’t have it both ways.

“Hogfather” is and remains nearly a perfect thing.

Huh. Well that's never happened before…

From the W65C816S data sheet.

Am I crazy, or would this seem to imply that I could use the BE input wired to PHI2 to tri-state the data pins (and address pins) on the CPU when PHI2 is low, thus preventing the "bank address" from ever hitting the bus at all?

The FB group is legitimate, but the banner image is definitely not. The more you look at it the worse it gets.

@thomasfuchs @Recta_Pete I need to go dig out my OD&D booklets, inherited from my father in law, who bought them new. The very first version of D&D, little staple-bound black and white booklets.

CPU, RAM, ROM, and VERA. A minimal X16 subset. This I can build in short order.

It won't be binary compatible, it will barely even be a computer -- but its purpose is not to be a computer, but to test the viability of the use of the W65C816S with 16-bit addressing as a W65C02S replacement in an X16 clone design.