Public
- Public
- Network
- Groups
- Featured
- Popular
- People

2.15 Bus Enable (BE) The Bus Enable input signal allows external control of the Address and Data Buffers, as well as the RWB signal. With Bus Enable high, the RWB and Address Buffers are active. The Data/Address Buffers are active during the first half of every cycle and the second half of a write cycle. When BE is low, these buffers are disabled. Bus Enable is an asynchronous signal.

Download link

2.15 Bus Enable (BE) The Bus Enable input signal allows external control of the Address and Data Buffers, as well as the RWB signal. With Bus Enable high, the RWB and Address Buffers are active. The Data/Address Buffers are active during the first half of every cycle and the second half of a write cycle. When BE is low, these buffers are disabled. Bus Enable is an asynchronous signal.
https://cdn.masto.host/socstudio8502ca/media_attachments/files/111/559/792/261/406/210/original/857a75181585e53e.png

Notices where this attachment appears

Embed this notice
Studio 8502 :verified: (mos_8502@soc.studio8502.ca)'s status on Monday, 11-Dec-2023 13:11:52 JST Studio 8502 :verified:

From the W65C816S data sheet.
Am I crazy, or would this seem to imply that I could use the BE input wired to PHI2 to tri-state the data pins (and address pins) on the CPU when PHI2 is low, thus preventing the "bank address" from ever hitting the bus at all?

In conversation about a year ago from soc.studio8502.ca permalink