Notices by William D. Jones (cr1901@mastodon.social)

@atax1a @dalias @pinskia Sooooo many ppl should know better. But "nah, I'm built different."

Also randomly reminded that there was a 6502 assembler that fit into 2 kilobytes by first turning the assembled program into instructions for a VM. The VM then overwrites its own instructions one by one to form the actual 6502 instructions:

https://web.archive.org/web/20250902233415if_/http://6502.org/source/monitors/2ksa.pdf

Written by one Robert Ford Denison (this is the right person AFAICT- looks like he decided not to stick w/ computers) https://cbs.umn.edu/directory/r-ford-denison

This sucks... a long time ago, someone posted a photo of their father's handwritten listing of 6502 code. The listing had like 5 columns for: Label, Address, Instruction, Encoding, and Comment. It was a standard 8.5x11" sheet. Aaaand I can't find the photo for the life of me to try and make a template.

I have released Sentinel v0.1.0-beta.2.

Sentinel is my microcoded RISC-V CPU core written in Amaranth. It fits in ~1000 LUTs and ~400 FFs on an ice40 FPGA, and implements RV32I_Zicsr and the Machine Mode privileged spec, and passes the RISCOF and RISC-V Formal test suites.

Ready-to-use Verilog is available here: https://codeberg.org/cr1901/sentinel/releases/tag/v0.1.0-beta.2

Sentinel is also available on PyPI now: https://pypi.org/project/sentinel-cpu/

If you wish to play with the source, follow the Quick Quick Start:

https://codeberg.org/cr1901/sentinel

Public service idea: Send me your floppy disks for postage (to and from), and I'll send you the files via email or temporary storage (if I can read them).

@dalias Ahhh, someone here (that's not you :P) mentioned that musl is unaffected...

@dalias This is correct for most CPUs; the 68k saves enough of its internal state to the stack on interrupt to continue in the middle of an instruction. It's in the patent, supposedly*.

* Which, I did not read, and I've heard conflicting info over the years as to whether the patent correctly describes all the saved state.

#lazyweb Is it correct to say that the 68000 and 68008 only have atomic load/stores of 16-bit and 8-bits respectively*?

* Unlike most CPUs, an interrupt will pause the current instruction and continue from where it left off. But I haven't read the patent or RE'd microcode. So not clear to me if 68000 will wait to honor an interrupt until after an up-to-32-bit load/store completes.

Without getting into the weeds... the fact that a bunch of ppl are implementing the birthday field, specifically _now_, at this point in time, gives me the ick. Idk if I'd give it a second thought 10 years ago.

Not a parent, and prob never will be. So I don't think ppl should put stock in my opinion on parental controls. Tho I wish ppl would listen to those who _don't_ think of their parents highly more.

I moved my AT2XT keyboard converter firmware + PCB to Codeberg. Please give it a star for the dopamine hit if you like :D https://codeberg.org/cr1901/AT2XT

@dalias Non snarky response... REALLY?! Was it that impossible to comb through your sources by hand?!

@dalias I need to decide who I hate more: Facebook or AI :P

@dalias @bert_hubert @bpreneel PhotoDNA may be bad for the reasons you describe. But CSAM detection has a horrific emotional/psychological toll on people who review it. And, for better or worse, computers don't pay that toll. I don't have a solution. :/

@bert_hubert @bpreneel @dalias Okay, this is interesting to me. I thought PhotoDNA tech was sound and can detect CSAM modified from the database' fingerprints*. Guess I have some reading to do.

* I hope to God the tech isn't storing actual CSAM

@dalias @tomrittervg (What about telemetry off, opt-in? I have exactly one piece of software I wrote where telemetry would be useful. But I'd never make it on by default.

That being said, I found out very quickly that said software basically "only works on my machine", so I'd need to add lots of tracing and ask ppl to run it. I shouldn't have released it :'D...

https://github.com/cr1901/swmon)

@xeno @dalias When I say "the world needs more crappy C compilers to exist", this... is not what I had in mind :'D.

#lazyweb I'm sorry if this is a stupid q, but... if you do a _single_ sendto call, you can send a single UDP packet of up to 65535-minus-some-change, and IP frag/reassembly will ensure you either receive it in order, or not at all?

I.e. it's only with multiple sendto calls that you start having problems with UDP packets being received out of order?

(And if you do a single sendto call, the larger the packet, the more likely it'll be dropped due to reassembly timeout?)

@erincandescent I wrote a UDP layer for an existing RPC library. I assume that any RPC fits within a single UDP packet, any packet can be lost, and that any RPC call is idempotent (so I don't have to care about ACKs being lost). But out-of-order is not something I handle currently (the RPC layer has a user field that could allow it tho).

I was just mulling over increasing the arbitrary max payload len from 128 to some larger number < ~65536 that's still likely to be received.

#lazyweb What is the POSIXy term for "commands surrounded by curly braces" (NOT parentheses) in shell scripting?

@david_chisnall @momo @soatok What does FreeBSD use?

(Context: I only use GPG for password-store. It'd be nice to get off it, but Idk alternatives. And I'd somehow need to properly script a conversion.)