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I have released Sentinel v0.1.0-beta. For those not following along (this is a new thread for reach), Sentinel is my microcoded RISC-V CPU core in ~1000 LUTs on an ice40 FPGA. It implements RV32I_Zicsr and the Machine Mode privileged spec, and passes the RISCOF and RISC-V Formal test suites (as of end of 2023- needs updating).

I rewrote the README.md/quickstart. So if you have git and Python 3 installed, you can have a generated Verilog RISC-V core in 5-10 mins.

https://github.com/cr1901/sentinel/tree/v0.1.0-beta