How you know you're having a fun evening.
Notices by Andrew Zonenberg (azonenberg@ioc.exchange), page 15
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Tuesday, 06-Feb-2024 06:17:21 JST Andrew Zonenberg -
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Saturday, 03-Feb-2024 14:51:50 JST Andrew Zonenberg Microcontroller layout on the KU+ test board.
This is a STM32L431 in the UFBGA100 package (500 μm pitch).
It's not technically compatible with OSHPark rules (125 μm trace/space) as you need 100 μm trace/space to fan out the second ring of balls, but it's for such a short distance that I think there's a good chance I'll get away with it. This is a quick and dirty prototype and I only need one of the three boards to be usable anyway. And if the MCU doesn't work at all, the board will still be usable, it's just a bonus.
I'm not sure how you're *supposed* to use this without microvias since the nominal land size is 285 μm on 500 μm centers. That leaves only 215 μm routing channel width, enough for a single 71 μm trace with 71 μm clearance.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Friday, 26-Jan-2024 23:33:18 JST Andrew Zonenberg @dalias I want to say yes but the fact that you're asking has me wondering...
Is there some dark corner of the spec where they diverge if the expressions have side effects?
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Sunday, 21-Jan-2024 22:45:24 JST Andrew Zonenberg @dragosr Related: is anyone out there still providing standalone paid mail hosting? My current provider transitioned all of their accounts over to ms365 a few months ago and I'm... Not a fan. Looking to leave but gmail is obviously not any better.
Does anyone still offer hosted IMAP mail using a Linux based software stack?
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Sunday, 21-Jan-2024 22:45:23 JST Andrew Zonenberg @dragosr (365 did similar recently IIRC forcing oauth)
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Sunday, 21-Jan-2024 19:35:44 JST Andrew Zonenberg @ryanc Yeah I grok basic RSA.
But factoring algorithms more complex than the sieve of Erastothenes are a different story.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Sunday, 21-Jan-2024 19:35:43 JST Andrew Zonenberg @ryanc I'm not a cryptographer. I can flag obviously non constant time implementations and major footguns like using rand() for key material or encrypting data in ECB mode.
But actually going from, say, a reused ECDSA nonce to a practical break isn't something I have any idea how to do. And while I get the basics of linear and differential cryptanalysis, actually being able to use that to achieve a realistic speedup vs brute force on real world encraption is a different story.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Sunday, 21-Jan-2024 17:33:20 JST Andrew Zonenberg @ryanc Pretty sure they're still a thing. Or stopped being a thing pretty recently.
The IBM Blue Gene family for example was still being actively developed when I was an undergrad although I think it got axed when I was in grad school?
It was a distributed memory system like most modern supercomputers but had full custom interconnects for efficient MPI operations etc. And some pretty cool compartmentalizion and segmentation capabilities for running many small problems at once if you didn't need all... 32K cores for the BG/L we had at the time iirc?
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Sunday, 21-Jan-2024 17:22:52 JST Andrew Zonenberg @ryanc Interesting, will look them up when I get a chance.
I'm much more familiar with going after symmetric crypto than asymmetric. Factorization breaks my brain and ECC is even worse.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Sunday, 21-Jan-2024 17:17:47 JST Andrew Zonenberg @ryanc Oh, apple II? I was assuming we were comparing a big pile of modern cloud hardware against the big iron of the days, something like a cray 1 (80 MHz 64-bit processor with 8 MB of RAM).
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Sunday, 21-Jan-2024 14:01:54 JST Andrew Zonenberg @ryanc Interesting. So did scalable factoring algorithms just not exist back then?
I assumed (perhaps incorrectly) that GNFS had been known for decades and it was just a matter of throwing more cores and memory at it to speed it up, and maybe small improvements in taking advantage of modern CPU microarchitecutres etc.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Sunday, 21-Jan-2024 13:55:12 JST Andrew Zonenberg @ryanc Yeah what I mean is, if you ran a 1970s era parallel factoring algorithm on modern hardware how much slower would it be than current gen GNFS?
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Sunday, 21-Jan-2024 12:37:25 JST Andrew Zonenberg @ryanc How much of that improvement in speed was computing power and how much was progress in factoring techniques?
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Tuesday, 16-Jan-2024 06:10:50 JST Andrew Zonenberg Ah, cities. Like tigers, magnificent things.
Like tigers, best viewed from a distance :)
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Tuesday, 16-Jan-2024 06:09:45 JST Andrew Zonenberg No go, it didn't attach. I guess that's better than overcooking and damaging the FPGA?
Back in the oven for another round.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Tuesday, 16-Jan-2024 06:09:44 JST Andrew Zonenberg Welp. I don't think they're supposed to do that.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Tuesday, 16-Jan-2024 06:09:44 JST Andrew Zonenberg This time I added witness solder on Kapton tape pads on both the FPGA package and the fixture. They melted quite a bit later than the adjacent board did.
Gave it 45 sec after *they* melted and hopefully it's good. I don't want to put more thermal cycles on this chip than I have to. I've already violated the absolute max ratings enough :)
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Tuesday, 16-Jan-2024 06:09:43 JST Andrew Zonenberg Here we go again.
Wonder if it'll work after all this? Good practice if nothing else I guess.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Tuesday, 16-Jan-2024 06:09:43 JST Andrew Zonenberg OK, cleaned up the gunk and re-tinned the pads with an iron (in case there were any issues with residue or something).
Time to try again.
This time on a scrap PCB to prevent any weirdness from the ridged tray I had it on last time. Maybe a bit more generous on the flux too?
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Tuesday, 16-Jan-2024 06:09:42 JST Andrew Zonenberg Cleaned off the paper, looks like a bunch of the balls around the edges did attach OK.
I wonder if my problem is not enough airflow under the chip? They do talk about that being important in the other process guidelines I found after some more research.
Maybe instead of putting this on a solid tray I should try putting it on the wire oven rack directly or something.