I normally gauge BGA reflow by watching the solder turn shiny and the chip drop, but that's not possible in this setup.
So I squirted some SAC305 paste on a witness board next to the fixture and gave it about 45 seconds after that melted. Hopefully it was enough, we'll find out when it cools.
After putting the preform in the fixture (ball side up) all I need to do is smear flux evenly across the lands on the package (no photos since my gloves were all sticky) and put the FPGA on top.
Reballing fixture and 676 ball 1mm preforms came in.
I'll let the chip cook a bit more before reballing it as I'm not in a rush.
These are pretty cool and it's my first time using them although I've been aware of them for quite a while. Instead of using loose solder balls you just flux the entire chip and stick this preform on top of it then reflow upside down to attach the balls.
You then apply a bit of water to soften the carrier material and it comes off leaving perfectly positioned solder balls.
Definitely more expensive than doing it with a stencil and loose balls (I paid a few hundred bucks for the fixture and 25 preforms) but IMO worth it for salvaging pricier parts.
On something like the third or fourth hour of baking the FPGA. Threw in a desiccant pouch to reactivate it since I couldn't find any unused desiccant other than loose silica gel beads.
I think this one was pretty saturated, lol. My lab is around 37% RH right now which is lowish but clearly not low enough.
Side view of the package substrate. It's a fourteen layer board!
The overall construction is two sets of seven layers using very thin, light colored dielectric with no evident glass reinforcement (so likely some kind of fancy microwave laminate) on either side of a thick core using a more conventional woven glass-resin structure.
The glass in the core looks to be spread but it's otherwise unremarkable.
Ok so, I need to reball this thing and my supplies are coming later today.
Before I reflow it I should probably try to desiccate it a bit more though.
IPC guidelines seem to suggest I should bake for 9 hours at 125C but that's probably not practical given that my oven only runs for a max of an hour at a time and so I'd need to be around to reset every hour. But I'll do as many 1-hour cycles as I have time for before I reball tonight.
Bottom side substrate photo, mirrored so it lines up with the top-down view in the datasheet. Ball A1 in top left corner. Slightly overexposed on the top left but it'll do.
A few of the lands look to have small amounts of solder residue that I didn't quite clean off fully, so before I reball I'll inspect and possibly clean them up. Hard to tell exactly how much solder there is in this lighting.
There's also a scratch in the soldermask around the T-U 12-13 region. Shouldn't be a big problem but I might try to touch it up just to make sure I don't get any problems.
The substrate matches the ballout perfectly (further evidence the chip is real) although there are a few interesting things:
* The GTY refclks don't have ground plane cutouts around them for impedance matching, only the high speed SERDES
* There's a tiny single-pin ground island next to the VCCAUX_IO island. Why not just fill with VCCINT there?
* Most interestingly, the VCCO zone fills don't line up with the IO banks!
Doing a full chip bottom side substrate scan of the XCKU5P-2FFVB676I on the Labsmore X1.
I don't have a proper darkfield setup but find that pure metallurgical brightfield illumination works poorly on chip packages and PCBs. Here's the low angle LED lamp setup I'm experimenting with.
Hard to get good uniformity on larger samples but it works decently.
One of the items in this shipment is (allegedly) a Xilinx XCKU5P that was cheap on AliExpress. The guy who sent it to me did some preliminary dead bug proof of life testing so now it's got bypass caps and missing solder balls stuck to the bottom.
Going to try reballing the KU5P tonight using these and a stencil. We'll see how it goes... good chance it'll end badly but I'm not gonna get better at reballing without practice.
Actually whoops, these are 0.5mm balls and I really need 0.6 to do the job right. Ordered some as I didn't have any in stock.
Anyway, I figure it's worth trying. This chip has been through hell by this point, two of the GTY RX pads are damaged (but not completely gone - so may still make contact just mechanically less robust).
I'm now thinking of making a little OSHPark test board that basically hooks up power, JTAG, cooling, and breaks out some of the SERDES so I can play with it, but not a whole lot else. Not sure I'd trust it on the BERT (which is still happening, but likely not with this physical chip).
My balls came! 0.6mm SAC305 solder spheres, a more reasonable 25K vs the 250K jar of 0.5mm that I'll never use (not that I expect to use 25K either but hey it was cheaper).
Always interesting to see them charge up and repel when you shake the container.
Cleaned off the paper, looks like a bunch of the balls around the edges did attach OK.
I wonder if my problem is not enough airflow under the chip? They do talk about that being important in the other process guidelines I found after some more research.
Maybe instead of putting this on a solid tray I should try putting it on the wire oven rack directly or something.
This time I added witness solder on Kapton tape pads on both the FPGA package and the fixture. They melted quite a bit later than the adjacent board did.
Gave it 45 sec after *they* melted and hopefully it's good. I don't want to put more thermal cycles on this chip than I have to. I've already violated the absolute max ratings enough :)