No go same failure mode. Preform expanded and sagged away from the BGA causing center balls to not make contact.
This chip might end up becoming microscope food. I'll play with it more but it's been through a lot of oven cycles now.
No go same failure mode. Preform expanded and sagged away from the BGA causing center balls to not make contact.
This chip might end up becoming microscope food. I'll play with it more but it's been through a lot of oven cycles now.
Or give up on preforms and do it the hard way.
Nope same issue with preform sagging.
Tempted to try upside down, it can't be worse than the proper way right?
My balls came! 0.6mm SAC305 solder spheres, a more reasonable 25K vs the 250K jar of 0.5mm that I'll never use (not that I expect to use 25K either but hey it was cheaper).
Always interesting to see them charge up and repel when you shake the container.
Actually whoops, these are 0.5mm balls and I really need 0.6 to do the job right. Ordered some as I didn't have any in stock.
Anyway, I figure it's worth trying. This chip has been through hell by this point, two of the GTY RX pads are damaged (but not completely gone - so may still make contact just mechanically less robust).
I'm now thinking of making a little OSHPark test board that basically hooks up power, JTAG, cooling, and breaks out some of the SERDES so I can play with it, but not a whole lot else. Not sure I'd trust it on the BERT (which is still happening, but likely not with this physical chip).
And if you jiggle the jar just right they "anneal" and form a hexagonal close packed "crystal" with large grains and occasional dislocations.
Best fit stencil i had was one row of balls too small so i have to hand place the outer ring. A dozen or so stuck to the stencil when i removed it.
Tweezer time...
Going to try reballing the KU5P tonight using these and a stencil. We'll see how it goes... good chance it'll end badly but I'm not gonna get better at reballing without practice.
The other big question of course is how many will move around and need to be cleaned up post reflow... I don't expect perfect results but can hope :)
Took a break to let my hand rest and counted the voids while I was waiting. 63 missing balls now missing out of 676.
25 left and I need to stretch my hand out again. Looks like a few sections are a bit light on flux, hopefully they reflow OK.
Also found that the AF19 land still has quite a bit of solder on it, hopefully the ball doesn't move around much (or get too giant).
All done and in the oven. Here goes...
One of the items in this shipment is (allegedly) a Xilinx XCKU5P that was cheap on AliExpress. The guy who sent it to me did some preliminary dead bug proof of life testing so now it's got bypass caps and missing solder balls stuck to the bottom.
Let's clean it up.
Today is a good day.
Doing a full chip bottom side substrate scan of the XCKU5P-2FFVB676I on the Labsmore X1.
I don't have a proper darkfield setup but find that pure metallurgical brightfield illumination works poorly on chip packages and PCBs. Here's the low angle LED lamp setup I'm experimenting with.
Hard to get good uniformity on larger samples but it works decently.
For example, on the substrate the VCCO_66 zone fill is a rectangle spanning A21 to J26.
But A21-A25 are in bank 67, not bank 66! So a significant number of the IOs surrounded by VCCO_66 are not actually powered by VCCO_66.
I wonder why this was done?
Bottom side substrate photo, mirrored so it lines up with the top-down view in the datasheet. Ball A1 in top left corner. Slightly overexposed on the top left but it'll do.
A few of the lands look to have small amounts of solder residue that I didn't quite clean off fully, so before I reball I'll inspect and possibly clean them up. Hard to tell exactly how much solder there is in this lighting.
There's also a scratch in the soldermask around the T-U 12-13 region. Shouldn't be a big problem but I might try to touch it up just to make sure I don't get any problems.
The substrate matches the ballout perfectly (further evidence the chip is real) although there are a few interesting things:
* The GTY refclks don't have ground plane cutouts around them for impedance matching, only the high speed SERDES
* There's a tiny single-pin ground island next to the VCCAUX_IO island. Why not just fill with VCCINT there?
* Most interestingly, the VCCO zone fills don't line up with the IO banks!
Ok so, I need to reball this thing and my supplies are coming later today.
Before I reflow it I should probably try to desiccate it a bit more though.
IPC guidelines seem to suggest I should bake for 9 hours at 125C but that's probably not practical given that my oven only runs for a max of an hour at a time and so I'd need to be around to reset every hour. But I'll do as many 1-hour cycles as I have time for before I reball tonight.
Side view of the package substrate. It's a fourteen layer board!
The overall construction is two sets of seven layers using very thin, light colored dielectric with no evident glass reinforcement (so likely some kind of fancy microwave laminate) on either side of a thick core using a more conventional woven glass-resin structure.
The glass in the core looks to be spread but it's otherwise unremarkable.
On something like the third or fourth hour of baking the FPGA. Threw in a desiccant pouch to reactivate it since I couldn't find any unused desiccant other than loose silica gel beads.
I think this one was pretty saturated, lol. My lab is around 37% RH right now which is lowish but clearly not low enough.
Security and open source at the hardware/software interface. Embedded sec @ IOActive. Lead dev of ngscopeclient/libscopehal. GHz probe designer. Open source networking hardware. "So others may live"Toots searchable on tootfinder.
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