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  1. Embed this notice
    Mikoto BSD (mikoto@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:00:37 JST Mikoto BSD Mikoto BSD
    the new framework mini pc thing honestly seems a bit weird in comparison to the rest of the rest of their lineup, like it's way less upgradable than everything else
    In conversation about 3 months ago from akko.wtf permalink
    • Embed this notice
      Mikoto BSD (mikoto@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:00:35 JST Mikoto BSD Mikoto BSD
      in reply to
      • Wolf480pl
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @novenary @wolf480pl LPCAMM2 is supposed to close the gap with more optimal trace routing compared to the traditional DIMM form factor. It does use the same chips and protocol as soldered on LPDDR chips.
      In conversation about 3 months ago permalink
      Haelwenn /элвэн/ :triskell: likes this.
    • Embed this notice
      Mikoto BSD (mikoto@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:00:36 JST Mikoto BSD Mikoto BSD
      in reply to
      • Wolf480pl

      @wolf480pl that’s what I’ve been wondering too

      An interesting quote from an Ars Technica article covering the news:

      “To enable the massive 256GB/s memory bandwidth that Ryzen AI Max delivers, the LPDDR5x is soldered,” writes Framework CEO Nirav Patel in a post about today’s announcements. “We spent months working with AMD to explore ways around this but ultimately determined that it wasn’t technically feasible to land modular memory at high throughput with the 256-bit memory bus. Because the memory is non-upgradeable, we’re being deliberate in making memory pricing more reasonable than you might find with other brands.”

      Makes me wonder if the memory speed is the reason they weren’t able to go with LPCAMM2 (since that currently seems to only reach ~7200 MT/s)

      In conversation about 3 months ago permalink
    • Embed this notice
      [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: (novenary@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:00:36 JST [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      in reply to
      • Wolf480pl
      @mikoto @wolf480pl that's kinda the thing with soldered RAM, it sucks, but it's also the only way to get LPDDR which is *way* faster than regular DDR precisely because it's soldered, actually faster than desktop memory too
      same reason why GPUs have always had soldered memory
      In conversation about 3 months ago permalink
    • Embed this notice
      Wolf480pl (wolf480pl@mstdn.io)'s status on Wednesday, 26-Feb-2025 07:00:37 JST Wolf480pl Wolf480pl
      in reply to

      @mikoto I wonder if they could've used LPCAMM2 memory...

      In conversation about 3 months ago permalink
    • Embed this notice
      Surströmming (selfhost arc) (xian@ak.kazuma.family)'s status on Wednesday, 26-Feb-2025 07:01:55 JST Surströmming (selfhost arc) Surströmming (selfhost arc)
      in reply to
      • Wolf480pl
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @wolf480pl @mikoto @novenary the ps1 had enough memory, we need to go back

      this is overkill
      In conversation about 3 months ago permalink
      Haelwenn /элвэн/ :triskell: likes this.
    • Embed this notice
      Wolf480pl (wolf480pl@mstdn.io)'s status on Wednesday, 26-Feb-2025 07:01:56 JST Wolf480pl Wolf480pl
      in reply to
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:

      @mikoto @novenary
      > FBDIMM

      hehe reminds me of the goo^W old PowerEdge 1950

      In conversation about 3 months ago permalink
    • Embed this notice
      Mikoto BSD (mikoto@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:01:57 JST Mikoto BSD Mikoto BSD
      in reply to
      • Wolf480pl
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:

      @novenary @wolf480pl serial ram is a thing, though most suffer from additional latency probably from SerDes stuff (you do have to convert back to parallel at some point).

      Intel tried with FBDIMMs, and there is also CXL as well, but the former failed spectacularly and the latter is only really used in the enterprise.

      In conversation about 3 months ago permalink
    • Embed this notice
      [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: (novenary@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:01:58 JST [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      in reply to
      • Wolf480pl
      @wolf480pl @mikoto eh, it's still feasible, we've learned to push much higher bandwidths over much longer links, albeit for serial connections
      that's kinda the whole problem with memory, it's an extremely wide parallel bus and routing that on a PCB while maintaining ludicrous speeds is the actual challenge
      the width of the memory bus on that thing is mid-range GPU tier, equivalent to quad channel DIMMs and also to what apple ships with their mac SoPs
      I imagine fitting two LPCAMM2 modules (they're apparently 128 bit wide) on a mini ITX board with such a huge chip might have been a challenge, or some other factor kept them from doing it
      In conversation about 3 months ago permalink
    • Embed this notice
      Mikoto BSD (mikoto@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:01:59 JST Mikoto BSD Mikoto BSD
      in reply to
      • Wolf480pl
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @novenary @wolf480pl there probably is still some level of inefficiency that comes with having to still have some sort of removable contact as opposed to using solder
      In conversation about 3 months ago permalink
    • Embed this notice
      Wolf480pl (wolf480pl@mstdn.io)'s status on Wednesday, 26-Feb-2025 07:01:59 JST Wolf480pl Wolf480pl
      in reply to
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:

      @mikoto @novenary it's not instead of solder, it's in addition to solder. One more connection point, which - depending on how precisely it's made and how good a contact there is - might cause signal reflections. AFAIU that might result in some higher speeds not working.

      In conversation about 3 months ago permalink
    • Embed this notice
      Haelwenn /элвэн/ :triskell: (lanodan@queer.hacktivis.me)'s status on Wednesday, 26-Feb-2025 07:04:38 JST Haelwenn /элвэн/ :triskell: Haelwenn /элвэн/ :triskell:
      in reply to
      • Wolf480pl
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @wolf480pl @mikoto @xian @novenary Would be quite funny if we'd end up going back to something like cache memory separated from the CPU (either as like cache on motherboard or on a CPU+Cache module board).
      In conversation about 3 months ago permalink
    • Embed this notice
      Mikoto BSD (mikoto@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:04:39 JST Mikoto BSD Mikoto BSD
      in reply to
      • Wolf480pl
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @wolf480pl @xian @novenary seen some people reporting that it does run better on x3d cpus
      In conversation about 3 months ago permalink
    • Embed this notice
      Wolf480pl (wolf480pl@mstdn.io)'s status on Wednesday, 26-Feb-2025 07:04:39 JST Wolf480pl Wolf480pl
      in reply to
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:

      @mikoto @xian @novenary
      Most games do.
      The thing with Tarkov is that, allegedly, it has huge frame latency spikes on anything that doesn't have 96MB of L3 cache :D

      In conversation about 3 months ago permalink
    • Embed this notice
      Mikoto BSD (mikoto@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:04:40 JST Mikoto BSD Mikoto BSD
      in reply to
      • Wolf480pl
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @wolf480pl @xian @novenary Cities Skylines
      In conversation about 3 months ago permalink
    • Embed this notice
      Wolf480pl (wolf480pl@mstdn.io)'s status on Wednesday, 26-Feb-2025 07:04:40 JST Wolf480pl Wolf480pl
      in reply to
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:

      @mikoto @xian @novenary
      really? Cities Skylines also requires an X3D CPU?

      In conversation about 3 months ago permalink
    • Embed this notice
      Wolf480pl (wolf480pl@mstdn.io)'s status on Wednesday, 26-Feb-2025 07:04:41 JST Wolf480pl Wolf480pl
      in reply to
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:

      @xian @mikoto @novenary Tarkov :P

      In conversation about 3 months ago permalink
    • Embed this notice
      Surströmming (selfhost arc) (xian@ak.kazuma.family)'s status on Wednesday, 26-Feb-2025 07:04:42 JST Surströmming (selfhost arc) Surströmming (selfhost arc)
      in reply to
      • Wolf480pl
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @novenary @mikoto @wolf480pl who even needs more than 32mb sram smh
      In conversation about 3 months ago permalink
    • Embed this notice
      [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: (novenary@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:04:43 JST [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      in reply to
      • Wolf480pl
      @mikoto @wolf480pl that's an interesting design, looks like a huge upgrade over DIMMs, I wonder if it's gonna take off
      In conversation about 3 months ago permalink
    • Embed this notice
      Mikoto BSD (mikoto@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:06:06 JST Mikoto BSD Mikoto BSD
      in reply to
      • Haelwenn /элвэн/ :triskell:
      • Wolf480pl
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @lanodan @xian @novenary @wolf480pl slot 1 holds a special place in my heart as that's what my first computer had
      In conversation about 3 months ago permalink
      Haelwenn /элвэн/ :triskell: likes this.
    • Embed this notice
      Haelwenn /элвэн/ :triskell: (lanodan@queer.hacktivis.me)'s status on Wednesday, 26-Feb-2025 07:07:43 JST Haelwenn /элвэн/ :triskell: Haelwenn /элвэн/ :triskell:
      in reply to
      • Wolf480pl
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @mikoto @xian @novenary @wolf480pl IIRC some Sun Workstations also had CPU module boards.
      In conversation about 3 months ago permalink
    • Embed this notice
      Wolf480pl (wolf480pl@mstdn.io)'s status on Wednesday, 26-Feb-2025 07:07:53 JST Wolf480pl Wolf480pl
      in reply to
      • Haelwenn /элвэн/ :triskell:
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:

      @lanodan @xian @mikoto @novenary IIRC the latest gen of AMD GPUs has cache in separate chiplets around the main GPU die....

      In conversation about 3 months ago permalink
      Haelwenn /элвэн/ :triskell: likes this.
    • Embed this notice
      [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: (novenary@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:08:03 JST [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      in reply to
      • Haelwenn /элвэн/ :triskell:
      • Wolf480pl
      • Surströmming (selfhost arc)
      @lanodan @xian @mikoto @wolf480pl we kinda edged that with L4 cache at some point but it was just edram on the CPU substrate
      but otherwise I think it's unlikely that we'd return to something like that
      In conversation about 3 months ago permalink
    • Embed this notice
      Mikoto BSD (mikoto@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:08:03 JST Mikoto BSD Mikoto BSD
      in reply to
      • Haelwenn /элвэн/ :triskell:
      • Wolf480pl
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @novenary @lanodan @wolf480pl @xian technically the additional cache on x3d cpus is a separate die from the CPU, just attached in a special way
      In conversation about 3 months ago permalink
      Haelwenn /элвэн/ :triskell: likes this.
    • Embed this notice
      [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: (novenary@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:09:48 JST [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      in reply to
      @mikoto tbh it seems strange that they would go into that market when it's already well-covered, especially within their niche since diy builds are quite popular and there's a plethora of parts on the market

      considering the non-upgradability this only competes with things like NUC-style mini PCs, and the mac mini and studio I guess, but sticking their laptop board form factor inside of a quality metal case would have been good enough imo
      as it stands, itx is completely pointless for this, the pcie slot is what, x4? could easily have been m.2 instead
      In conversation about 3 months ago permalink
      Haelwenn /элвэн/ :triskell: likes this.
    • Embed this notice
      Haelwenn /элвэн/ :triskell: (lanodan@queer.hacktivis.me)'s status on Wednesday, 26-Feb-2025 07:14:52 JST Haelwenn /элвэн/ :triskell: Haelwenn /элвэн/ :triskell:
      in reply to
      • Haelwenn /элвэн/ :triskell:
      • Wolf480pl
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @mikoto @novenary @wolf480pl @xian In fact I wonder if Cache + CPU is what's going on with the Ultra 10 CPU board.
      sunu109-251506833.jpg
      In conversation about 3 months ago permalink

      Attachments


      1. https://queer.hacktivis.me/media/ac8ce6a7-1d3b-4ff5-b69f-f69e629a62e0/sunu109-251506833.jpg
    • Embed this notice
      Mikoto BSD (mikoto@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:16:45 JST Mikoto BSD Mikoto BSD
      in reply to
      • Haelwenn /элвэн/ :triskell:
      • Wolf480pl
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @lanodan @xian @novenary @wolf480pl seemed to be pretty common when people discovered having cache closer to the cpu was a good idea but haven't figured out how to have it on the same die
      In conversation about 3 months ago permalink
      Haelwenn /элвэн/ :triskell: likes this.
    • Embed this notice
      Haelwenn /элвэн/ :triskell: (lanodan@queer.hacktivis.me)'s status on Wednesday, 26-Feb-2025 07:55:55 JST Haelwenn /элвэн/ :triskell: Haelwenn /элвэн/ :triskell:
      in reply to
      • Ignas Kiela
      • Wolf480pl
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @ignaloidas @wolf480pl @mikoto @novenary @xian Sure for L1…L3 cache but L4 seems like the kind of thing that could be right next to the CPU to avoid needing a massive die.
      In conversation about 3 months ago permalink
    • Embed this notice
      Ignas Kiela (ignaloidas@not.acu.lt)'s status on Wednesday, 26-Feb-2025 07:55:56 JST Ignas Kiela Ignas Kiela
      in reply to
      • Haelwenn /элвэн/ :triskell:
      • Wolf480pl
      • Surströmming (selfhost arc)
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:

      @lanodan@queer.hacktivis.me @wolf480pl@mstdn.io @mikoto@akko.wtf @xian@ak.kazuma.family @novenary@akko.wtf while cache kinda makes sense to have separate from a process perspective (SRAM doesn't really scale and other stuff), you really want a low-latency, high-bandwidth connection to it. It's over to 1TB/s in modern CPU's, and that's real hard to put away from the CPU without introducing a bunch of latency.

      In conversation about 3 months ago permalink
    • Embed this notice
      Wolf480pl (wolf480pl@mstdn.io)'s status on Wednesday, 26-Feb-2025 07:56:06 JST Wolf480pl Wolf480pl
      in reply to
      • LisPi
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:

      @novenary @mikoto @lispi314
      > for repair, I don't really see anything wrong with leaving that up to specialists

      Except that causes a lot of downtime. Unless you have a whole spare computer.

      In conversation about 3 months ago permalink
      Haelwenn /элвэн/ :triskell: likes this.
    • Embed this notice
      [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: (novenary@akko.wtf)'s status on Wednesday, 26-Feb-2025 07:56:07 JST [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      in reply to
      • Wolf480pl
      • LisPi
      @lispi314 @mikoto @wolf480pl imo repair and upgradability are separate concerns even if they overlap to some extent

      the latter simply shouldn't be necessary, after all artificial market segmentation for electronics is a scam to charge you more for hardware that barely costs more to produce, there is no reason to sell crippled CPUs and machines with less than the maximum supported amount of memory

      for repair, I don't really see anything wrong with leaving that up to specialists
      there is a real engineering trade-off here, they're not just deliberately making it harder to repair even if it happens to be convenient for them
      similar situation for combustion engines with cylinder coatings replacing cast iron sleeves in aluminium blocks, which makes them prohibitively expensive to rebuild, but unlocks performance *and* makes them significantly more durable!

      the sad reality is that capitalism will not do the right thing here anyway, and in most cases perfectly repairable machines end up in the landfill/junkyard regardless of user serviceability for a whole host of reasons, including user miseducation and obsolescence, or insurance writing off vehicles way too liberally
      In conversation about 3 months ago permalink
    • Embed this notice
      LisPi (lispi314@udongein.xyz)'s status on Wednesday, 26-Feb-2025 07:56:08 JST LisPi LisPi
      in reply to
      • Wolf480pl
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @novenary @wolf480pl @mikoto That would be okay if they also sold the microsoldering kit alongside the computer, since it's going to be necessary to upgrade it at all.

      Because of course they designed that to be upgradable, right? They didn't just commit to generating e-waste unnecessarily, right?

      Just as importantly as upgrades though, soldered-on RAM /cannot be replaced easily/ which is a major problem if any of it goes bad. Especially if it's not ECC memory.
      In conversation about 3 months ago permalink
    • Embed this notice
      Haelwenn /элвэн/ :triskell: (lanodan@queer.hacktivis.me)'s status on Wednesday, 26-Feb-2025 07:58:35 JST Haelwenn /элвэн/ :triskell: Haelwenn /элвэн/ :triskell:
      in reply to
      • Wolf480pl
      • LisPi
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @wolf480pl @novenary @mikoto @lispi314 Plus there's the issue of finding said specialists, as the vast majority of computer "repair" shops just do dust cleaning, parts swap and windows reinstalls.
      In conversation about 3 months ago permalink
    • Embed this notice
      [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: (novenary@akko.wtf)'s status on Wednesday, 26-Feb-2025 08:11:38 JST [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      in reply to
      • Wolf480pl
      • LisPi
      @lispi314 @mikoto @wolf480pl >Those specialists cost a fortune (often enough to make buying a new machine more palatable) when they're available at all (which they aren't here, I'd need to commute for a long time or ship the machine at considerable expense). It is also concerning that so much stateful hardware (but hard to reflash by users) remains on a machine, such that if the repair specialist is malicious, they can get up to shenanigans nearly undetectably.

      a huge part of the problem here is how uncommon board repair is, and this won't improve without manufacturers' cooperation

      also, I don't really believe that memory or CPU failure is necessarily more common than other components that are *always* soldered down (ignoring design flaws like bumpgate or Intel's modern CPUs)
      for example I would say that after storage (for which modularity does not imply any trade-offs, soldered SSDs are plain sabotage), power issues are likely the most common failure mode, yet you don't see motherboards with modular VRMs, and those would be infinitely easier to implement than any high speed data bus

      that said, serviceability is obviously a good thing, and LPCAMM proves that sometimes it's just that the industry didn't bother optimizing for it when making trade-offs
      as far as that framework board is concerned, I honestly don't know what kept them from using it, and I don't think we'll find out if they don't publish any details
      it's still a very strange product
      In conversation about 3 months ago permalink
      Haelwenn /элвэн/ :triskell: likes this.
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      LisPi (lispi314@udongein.xyz)'s status on Wednesday, 26-Feb-2025 08:11:40 JST LisPi LisPi
      in reply to
      • Wolf480pl
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @novenary @wolf480pl @mikoto > after all artificial market segmentation for electronics is a scam to charge you more for hardware that barely costs more to produce, there is no reason to sell crippled CPUs and machines with less than the maximum supported amount of memory

      Agreed.

      > for repair, I don't really see anything wrong with leaving that up to specialists

      Those specialists cost a fortune (often enough to make buying a new machine more palatable) when they're available at all (which they aren't here, I'd need to commute for a long time or ship the machine at considerable expense). It is also concerning that so much stateful hardware (but hard to reflash by users) remains on a machine, such that if the repair specialist is malicious, they can get up to shenanigans nearly undetectably.

      > the sad reality is that capitalism will not do the right thing here anyway, and in most cases perfectly repairable machines end up in the landfill/junkyard regardless of user serviceability for a whole host of reasons, including user miseducation and obsolescence, or insurance writing off vehicles way too liberally

      That is unfortunately true.
      In conversation about 3 months ago permalink
    • Embed this notice
      [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: (novenary@akko.wtf)'s status on Wednesday, 26-Feb-2025 08:47:22 JST [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      in reply to
      • Wolf480pl
      • LisPi
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      @wolf480pl @lispi314 @mikoto like, for CPUs, the lower you go down the tier list, the less sense the SKUs make rationally

      for example it's well-known that when Ryzen 3000 launched, the yield rate was so good that they actually had to deliberately cripple healthy dies to meet demand for 6-core chiplets
      which means that anything with less than 6 cores should never have existed, yet they sold quad cores and other weird configurations anyway

      and of course, the actual production cost of those chips is only a fraction of the retail price, and it certainly doesn't justify the roughly linear scaling of the price with specs
      In conversation about 3 months ago permalink
      Haelwenn /элвэн/ :triskell: likes this.
    • Embed this notice
      [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: (novenary@akko.wtf)'s status on Wednesday, 26-Feb-2025 08:47:23 JST [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic: [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:
      in reply to
      • Wolf480pl
      • LisPi
      @wolf480pl @mikoto @lispi314 yeah that's mostly a hypothetical/ideal situation I'm talking about here
      like I said, it makes no sense for OEMs to build machines that aren't the best possible spec other than driving sales, and as consumers we have absolutely no say over the matter
      this is me lamenting the status quo
      In conversation about 3 months ago permalink
    • Embed this notice
      Wolf480pl (wolf480pl@mstdn.io)'s status on Wednesday, 26-Feb-2025 08:47:24 JST Wolf480pl Wolf480pl
      in reply to
      • LisPi
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:

      @novenary @mikoto @lispi314
      And regarding upgradability - where I live, 128 GB of cheapest DDR5 SODIMM costs as much as a Radeon RX 6700. So I think with upgradable RAM, ir makes sense to buy less initially.

      But if I could get 128GB of soldered DDR5 for the price of 32GB SODIMM, I'd happily go with the soldered RAM

      In conversation about 3 months ago permalink
    • Embed this notice
      Wolf480pl (wolf480pl@mstdn.io)'s status on Wednesday, 26-Feb-2025 08:51:47 JST Wolf480pl Wolf480pl
      in reply to
      • LisPi
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:

      @novenary @mikoto @lispi314
      In an LTT video, a guy from Framework said that when they asked AMD about LPCAMM, AMD ran a lot of simulations and concluded that the 256-bit memory bus is too wide for that to work. I don't remember if signal integrity was mentioned, but I'd expect that's what would cause the problem.

      In conversation about 3 months ago permalink
      Haelwenn /элвэн/ :triskell: likes this.
    • Embed this notice
      Ignas Kiela (ignaloidas@not.acu.lt)'s status on Wednesday, 26-Feb-2025 11:21:43 JST Ignas Kiela Ignas Kiela
      in reply to
      • Wolf480pl
      • LisPi
      • [GRLC] (⁠^⁠.⁠_⁠.⁠^⁠)⁠ノ :neocat_flag_sapphic:

      @novenary@akko.wtf @lispi314@udongein.xyz @mikoto@akko.wtf @wolf480pl@mstdn.io yet you don't see motherboards with modular VRMs, and those would be infinitely easier to implement than any high speed data busrespectfully, no. Power delivery networks for modern high-power chips are very complex, with high currents (60+A), and also fairly high frequencies because the power draw frequency generally matches the processors frequency. Dealing with tens to hundreds of amps together with fairly high frequency (even with filtering on the board, it's still in at least tens of megahertz) is tough for connectors, and you'd prefer not to have that problem where you don't strictly need to.

      In conversation about 3 months ago permalink
      Haelwenn /элвэн/ :triskell: likes this.

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