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Haelwenn /элвэн/ :triskell: (lanodan@queer.hacktivis.me)'s status on Wednesday, 26-Feb-2025 07:04:38 JST Haelwenn /элвэн/ :triskell:
@wolf480pl @mikoto @xian @novenary Would be quite funny if we'd end up going back to something like cache memory separated from the CPU (either as like cache on motherboard or on a CPU+Cache module board).