@dalias yeah it's fricking great.
As usual we've got Claire Wolf to thank here. It's a clever trick -- given the reverse-engineered the ICE40 bitstream format, and some (very mild) assumptions about how Yosys maps big RAMs onto FPGA BRAMs, you can find RAMs by parsing the bitstream and just rewrite them in-place.
The "Project X-Ray" reverse-engineering of the Xilinx 7-series bitstream should enable this same thing for Xilinx parts using Yosys, but I'm not sure if they've done it yet.