@sun @fiore @Suiseiseki @nyanide @meso
The speed of modern CPUs that we take for granted comes from these sources:
- a high performance DRAM controller
- a large hierarchical cache
- out-of-order execution
- super-scalar or parallel execution
- a high clock rate
- all of this is underpinned by a small feature size process and a large gate budget

A typical RISC-V aims for a low cost implementation that lacks these elements. Without them, you're basically making a 200 MHz, 5 to 10 pipeline stage CPU. I'm generalizing it a lot, but you're ending with something like MicroSPARC-II or thereabout.

I heard about high performance RISC-V implementations aimed at hyperscalers, but I've never seen one in person.