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   Ryan Castellucci (they/them) :nonbinary_flag: (ryanc@infosec.exchange)'s status on Sunday, 15-Feb-2026 00:35:15 JST Ryan Castellucci (they/them) :nonbinary_flag:

   Saw a blog post titled "How many registers does an x86-64 CPU have?" and my immediate thought was "it's impossible to know and a sin to ask".

   If you think the answer is 16, by the way, no it is not.

   • Embed this notice
     Cat 🐈🥗 (D.Burch) (catsalad@infosec.exchange)'s status on Sunday, 15-Feb-2026 00:47:38 JST Cat 🐈🥗 (D.Burch)

     in reply to

     @ryanc Oh, that's easy!
     x86-64
     x86 = 64
     x = 64⁄86
     x = 32⁄43

     So it has at least 1.344 registers!

   • Embed this notice
     Ryan Castellucci (they/them) :nonbinary_flag: (ryanc@infosec.exchange)'s status on Sunday, 15-Feb-2026 00:51:56 JST Ryan Castellucci (they/them) :nonbinary_flag:

     in reply to

     • Graham Sutherland / Polynomial

     @gsuberland yup

   • Embed this notice
     Graham Sutherland / Polynomial (gsuberland@chaos.social)'s status on Sunday, 15-Feb-2026 00:51:57 JST Graham Sutherland / Polynomial

     in reply to

     @ryanc based on the reverse engineered microcode from Intel platforms we have RED unlock on I'd guess there are probably a hundred named internal microarchitectural registers at least (if we count unnamed we'll be here all week)

   • Embed this notice
     Graham Sutherland / Polynomial (gsuberland@chaos.social)'s status on Sunday, 15-Feb-2026 00:51:59 JST Graham Sutherland / Polynomial

     in reply to

     @ryanc yeah uhhh off the top of my head

     rax, rbx, rcx, rdx, r8-r15, rdi, rsi, rsp, rbp, rip and all the components thereof, and rflags

     zmm0-zmm??? (can't remember how many we have now) plus the ymm/xmm components.

     6 ye olde segment registers.

     gdtr, ldtr, idtr, and another I forgot the name of.

     maybe 5 control registers? they're numbered to 15 but most are reserved

     8 debug registers

     x87 FPU and MMX weirdness

     hundreds of MSRs, hundreds more if you count CPUID leaves

     plus internal regs

   • Embed this notice
     Ryan Castellucci (they/them) :nonbinary_flag: (ryanc@infosec.exchange)'s status on Sunday, 15-Feb-2026 00:52:57 JST Ryan Castellucci (they/them) :nonbinary_flag:

     in reply to

     • Cat 🐈🥗 (D.Burch)

     @catsalad your logic is flawless

   • Embed this notice
     Rich Felker (dalias@hachyderm.io)'s status on Sunday, 15-Feb-2026 02:02:27 JST Rich Felker

     in reply to

     @ryanc It depends a lot on what you mean by registers and which execution domain you're talking about.

   • Embed this notice
     Ryan Castellucci (they/them) :nonbinary_flag: (ryanc@infosec.exchange)'s status on Sunday, 15-Feb-2026 02:23:39 JST Ryan Castellucci (they/them) :nonbinary_flag:

     in reply to

     • Rich Felker

     @dalias yes

   • Embed this notice
     Simon Zerafa (simonzerafa@infosec.exchange)'s status on Sunday, 15-Feb-2026 05:44:41 JST Simon Zerafa

     in reply to

     @ryanc

     African or European Registers? 🤔🤷♂️

   • Embed this notice
     David Chisnall (*Now with 50% more sarcasm!*) (david_chisnall@infosec.exchange)'s status on Sunday, 15-Feb-2026 06:31:06 JST David Chisnall (*Now with 50% more sarcasm!*)

     in reply to

     @ryanc Architectural registers, or are you counting rename registers as well?

     If it’s the former, the answer is: too many.

     If it’s the latter, the answer is: not enough.

   • Embed this notice
     Ryan Castellucci (they/them) :nonbinary_flag: (ryanc@infosec.exchange)'s status on Sunday, 15-Feb-2026 06:42:54 JST Ryan Castellucci (they/them) :nonbinary_flag:

     in reply to

     • David Chisnall (*Now with 50% more sarcasm!*)

     @david_chisnall we're counting whatever causes the .ost sanity damage

   • Embed this notice
     Ryan Castellucci (they/them) :nonbinary_flag: (ryanc@infosec.exchange)'s status on Sunday, 15-Feb-2026 06:43:22 JST Ryan Castellucci (they/them) :nonbinary_flag:

     in reply to

     • David Chisnall (*Now with 50% more sarcasm!*)

     @david_chisnall we're counting whatever causes the most sanity damage

   • Embed this notice
     David Chisnall (*Now with 50% more sarcasm!*) (david_chisnall@infosec.exchange)'s status on Sunday, 15-Feb-2026 06:45:07 JST David Chisnall (*Now with 50% more sarcasm!*)

     in reply to

     @ryanc Yes, you already said x86-64 in the initial post.

   • Embed this notice
     Ryan Castellucci (they/them) :nonbinary_flag: (ryanc@infosec.exchange)'s status on Sunday, 15-Feb-2026 07:35:23 JST Ryan Castellucci (they/them) :nonbinary_flag:

     in reply to

     • mcc

     @mcc I can't imagine it is, for sufficiently literal and pedantic meanings of "general".

   • Embed this notice
     mcc (mcc@mastodon.social)'s status on Sunday, 15-Feb-2026 07:35:24 JST mcc

     in reply to

     @ryanc Now, the mindmelting version of this question is: You are a virtual machine or something similar and you need to preserve the state of the currently executing thread for future resumption. Is this, in general, possible?

   • Embed this notice
     mx alex tax1a - 2020 (6) (atax1a@infosec.exchange)'s status on Sunday, 15-Feb-2026 09:40:34 JST mx alex tax1a - 2020 (6)

     in reply to

     RE: https://infosec.exchange/@atax1a/112924171213763471

     @ryanc

   • Embed this notice
     Simon Zerafa (simonzerafa@infosec.exchange)'s status on Sunday, 15-Feb-2026 16:35:44 JST Simon Zerafa

     in reply to

     @ryanc

     Bits in quick access,
     Moving through the pipeline fast,
     Logic starts right here.

     🙂🖖

   • Embed this notice
     Ryan Castellucci (they/them) :nonbinary_flag: (ryanc@infosec.exchange)'s status on Sunday, 26-Apr-2026 03:34:06 JST Ryan Castellucci (they/them) :nonbinary_flag:

     in reply to

     • Graham Sutherland / Polynomial
     • Job

     @vanderZwan @gsuberland it is a sin to ask

   • Embed this notice
     Job (vanderzwan@vis.social)'s status on Sunday, 26-Apr-2026 03:34:07 JST Job

     in reply to

     • Graham Sutherland / Polynomial

     @gsuberland @ryanc so the correct answer is "yes"?

   • Embed this notice
     Graham Sutherland / Polynomial (gsuberland@chaos.social)'s status on Sunday, 26-Apr-2026 03:34:09 JST Graham Sutherland / Polynomial

     in reply to

     @ryanc and that's if you only count the internal registers for the main x86-64 cores and the surrounding cache/memory architecture.

     if we include internal registers for UPI, PCIe, integrated graphics, TPM, IOMMU, VT-d/VT-x, and features like AMT and VROC, there's thousands of them.