Notices by niconiconi (niconiconi@mk.absturztau.be)

@puniko Good meownyaaaaaaaaaaaaaaa

@puniko Good meownyaaaaaaaaaaaaaa

@puniko Good meownyaaaaaaaaaaaaaaa

@puniko Some old historical documents in DjVu had the same problem.

"An error introduced by OCR scanning is sometimes termed a scanno (by analogy with the term typo)"LMAO :blobcatlul:

@whitequark@social.treehouse.systems I recently renewed a domain for 10+ years so people can still keep using it (via the DNS) until the singularity if I have a heart attack tomorrow.

@icedquinn@blob.cat There's new topo autorouter currently in development, funded by NLnet. https://codeberg.org/topola/topola

It's still pretty difficult to route a single-layer board with KiCad. Who still uses single-layer board these days? Pretty much everyone who does anything modern with a 2-layer PCB, the bottom layer is the EMC/RF ground plane, so there's only 1 effective layer. There really should be a "jumper manager" that allows you to add ad-hoc wires and THT/SMD resistors, perhaps with back-annotation. #electronics

@puniko Good meownyaaaaaaaaaaa

The John F. Kennedy Center is now called The Trump Kennedy Center, WTF?! :blobcatfacepalm: I thought it was an April Fool joke, but it's real?! :blobcatfacepalm: https://www.theguardian.com/us-news/2026/feb/01/kennedy-center-dc-closed-trump

@puniko Trying to emulate the NES cartridge mapper ASIC + ROM + RAM hardware in software using a fast microcontroller.

Optimizing IRQ latency on the STM32H743 @ 480 MHz, perhaps for NES ROM emulation... Best result so far: 100 nanoseconds input-to-output latency when the vector table and the IRQ handler are relocated to Tightly-Coupled Memory without making HAL calls. Not bad, but the GPIO controller (several buses away) looks like the real performance killer here. WARNING: buggy code, see correction https://mk.absturztau.be/notes/ajvb448y305b01i4. #electronics #STM32

Keep optimizing IRQ latency on the STM32H743 @ 480 MHz. Just enabled i-cache and d-cache, and the IRQ latency dropped from 100 ns to 70 ns. 🚀 But cache shouldn't work like this. So my code is still touching slow memory somewhere. The stack perhaps, which is still in "normal" RAM. The slow Flash perhaps also makes it slower to abort main() if an instruction is stuck in a wait state. Need to check everything carefully... #electronics #STM32

Keep optimizing IRQ latency on the STM32H743 @ 480 MHz. The 70 ns vs. 100 ns overhead mystery solved. I did not correctly relocate the vector table to Tightly-Coupled Memory properly, it was still in Flash. The STM32 HAL macro USER_VECT_TAB_ADDRESS is a flag, not a memory address! In fact, only several hardcoded addresses are available, a real user override is not provided (the name "user" is a lie). Solution: just change VTOR manually, don't trust the startup code. I'm now getting 70-ns IRQ without CPU cache. #electronics #STM32

I do not understand how the NES system bus works, even after reading multiple tutorials. Only one way to find out... #electronics #NES #NESdev

Q: What should you do when your application needs real-time control?
A: You start using an RTOS.
Q: What should you do when your application really needs real-time control?
A: You stop using an RTOS.

Everyone has a Glasgow Interface Explorer, meanwhile I just fired up my Bus Pirate v4 like some kind of a caveman. :woozy_baa:

@puniko :nikoni1:

@puniko Good meownyaaaaaaaaaaaaaaaa

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