Notices by Sun Microdevil Pte Ltd (koakuma@uwu.social)

cjara instance move :YEEEEEE:

@kaia Catching up with many folks in the so-called "developing countries" :02smile:

@a1ba Open midriff!

flandre :cirnothinking:

Nasi capcai Bangka + pangsit #MakanApaToday :blobcatreachmeltuwu:

@cell 30kg R18 doujinshi haul :cirnothinking:

@lain Bleisure

I need to be squeezed in a rush hour train

@q66 There'll be RISC-V big endian too dw :akkoderp:

@lkundrak @q66 The same reason as to why people do little endian SPARC :02lurk:

@lkundrak @q66 Can't say anything about the rest, but

> is there an actual little-endian sparc? (all i knew is that memory loads and stores can be little endian and that's about it)

Hardware-wise, yes, technially all SPARCs are bi-endian
You can set PSTATE.cle and PSTATE.tle to 1 and from that point on your processor should effectively become LE

However, all instruction words are to be encoded in BE, even when the CPU runs in LE mode :akkoderp:

Aside from that, there are variants of loads and stores that take explicit endianness parameter, and atomic CAS instructions always require endianness to be supplied explicitly

@q66 Fanfiction first, hardware can come later! :hehehe:

@lain I bet the Germans have some DIN rules regulating how much force the attachment needs to be able to withstand

@secalinum Cuddleable

@chjara Some fun thought about ads: it's not designed so that you want to buy it the moment you see it, it's designed to plant the knowledge of the brand so that when you do go shopping, your unconscious will pick the now-familiar name over unknown ones :02lurk:

@natalie I wish outages here is as short as that...

@kaia Chocoyogurt :cirnothinking:

@waifu Lots of manga...

Thorns :blobcatcamera:

Now back with #MakanApaToday included!

@dwarf @cell Can still use APSC lens at 26MP so it's like getting an A6700 included :cirnouwu: