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<blockquote style="position: relative; padding-left: 55px;"><section><a href="https://mastodon.gamedev.place/users/rygorous/statuses/114973321405581327">Fabian Giesen (rygorous@mastodon.gamedev.place)'s status on Tuesday, 05-Aug-2025 10:13:14 JST</a><a href="https://mastodon.gamedev.place/@rygorous" title="rygorous@mastodon.gamedev.place"><img src="https://gnusocial.jp/avatar/95257-48-20250601185436.webp" width="48" height="48" alt="Fabian Giesen" style="position: absolute; left: 0; top: 0;">Fabian Giesen</a><div><a href="https://gnusocial.jp/notice/10702710" rel="in-reply-to">in reply to</a><ul><li><li><a href="https://gnusocial.jp/user/296009" title="chrisvest@mastodon.social">Chris</a></li></ul></div></section><article><p><a href="https://mastodon.social/@chrisvest">@chrisvest</a> <a href="https://mastodon.social/@whitequark">@whitequark</a> honestly something derived from an actual normal ISA you've heard of sounds positively sane, these random microcontrollers have a long and proud history of running the most obscure stuff imaginable because usually someone picked whatever was cheap out of a bin 25 years ago.</p><p>E.g. Intel's Management Engine firmware used (long ago) to run on ARC cores <a href="https://en.wikipedia.org/wiki/ARC_(processor)" rel="nofollow">https://en.wikipedia.org/wiki/ARC_(processor)</a> - literally derived from the SNES SuperFX chip. Not making this up.</p></article><footer><a rel="bookmark" href="https://gnusocial.jp/conversation/5452783#notice-10702711">In conversation</a><time datetime="2025-08-05T10:13:14+09:00" title="Tuesday, 05-Aug-2025 10:13:14 JST">about a year ago</time> <span>from <span><a href="https://mastodon.gamedev.place/@rygorous/114973321405581327" rel="external" title="Sent from mastodon.gamedev.place via ActivityPub">mastodon.gamedev.place</a></span></span><a href="https://mastodon.gamedev.place/@rygorous/114973321405581327">permalink</a><h4>Attachments</h4><ol><li><article><header><div>Domain not in remote thumbnail source whitelist: login.wikimedia.org</div><h5><a href="https://en.wikipedia.org/wiki/ARC_(processor)">ARC (processor)</a></h5><div></div></header><div>Argonaut RISC Core (ARC) is a family of 32-bit and 64-bit reduced instruction set computer (RISC) central processing units (CPUs) originally designed by ARC International.
ARC processors are configurable and extensible for a wide range of uses in system on a chip (SoC) devices, including storage, digital home, mobile, automotive, and Internet of things (IoT) applications. They have been licensed by more than 200 organizations and are shipped in more than 1.5 billion products per year.
ARC processors employ the 16-/32-bit ARCompact compressed instruction set instruction set architecture (ISA) that provides good performance and code density for embedded and host SoC applications.History
The ARC concept was developed initially within Argonaut Games through a series of 3D pipeline development projects starting with the Super FX chip for the Super Nintendo Entertainment System.
In 1995, Argonaut was split into Argonaut Technologies Limited (ATL), which had a variety of technology projects, and Argonaut Software Limited (ASL).
At the start of 1996, the General Manager of...</div><footer></footer></article></li></ol></footer></blockquote>

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Fabian Giesen (rygorous@mastodon.gamedev.place)'s status on Tuesday, 05-Aug-2025 10:13:14 JSTFabian Giesen
in reply to
- ✧✦Catherine✦✧
- Chris
@chrisvest @whitequark honestly something derived from an actual normal ISA you've heard of sounds positively sane, these random microcontrollers have a long and proud history of running the most obscure stuff imaginable because usually someone picked whatever was cheap out of a bin 25 years ago.
E.g. Intel's Management Engine firmware used (long ago) to run on ARC cores https://en.wikipedia.org/wiki/ARC_(processor) - literally derived from the SNES SuperFX chip. Not making this up.
In conversationabout a year ago from mastodon.gamedev.placepermalink
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  ARC (processor)
  Argonaut RISC Core (ARC) is a family of 32-bit and 64-bit reduced instruction set computer (RISC) central processing units (CPUs) originally designed by ARC International. ARC processors are configurable and extensible for a wide range of uses in system on a chip (SoC) devices, including storage, digital home, mobile, automotive, and Internet of things (IoT) applications. They have been licensed by more than 200 organizations and are shipped in more than 1.5 billion products per year. ARC processors employ the 16-/32-bit ARCompact compressed instruction set instruction set architecture (ISA) that provides good performance and code density for embedded and host SoC applications. History The ARC concept was developed initially within Argonaut Games through a series of 3D pipeline development projects starting with the Super FX chip for the Super Nintendo Entertainment System. In 1995, Argonaut was split into Argonaut Technologies Limited (ATL), which had a variety of technology projects, and Argonaut Software Limited (ASL). At the start of 1996, the General Manager of...

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