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✧✦Catherine✦✧ (whitequark@mastodon.social)'s status on Tuesday, 05-Aug-2025 07:43:27 JST ✧✦Catherine✦✧

OH: "itanium larrabee"

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  Chris (chrisvest@mastodon.social)'s status on Tuesday, 05-Aug-2025 07:50:01 JST Chris
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  @whitequark can't decide if this is better or worse than the Intel NPU that's just an array of SPARC processors.
  
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  ✧✦Catherine✦✧ (whitequark@mastodon.social)'s status on Tuesday, 05-Aug-2025 07:54:04 JST ✧✦Catherine✦✧
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  @chrisvest which one? I vaguely recall
  
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  Chris (chrisvest@mastodon.social)'s status on Tuesday, 05-Aug-2025 07:54:37 JST Chris
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  @whitequark It's in Meteor Lake: https://chipsandcheese.com/p/intel-meteor-lakes-npu
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    Intel Meteor Lake’s NPU
    
    from Chester Lam
    
    AI is a hot topic and Intel doesn’t want to be left out, so their Meteor Lake mobile processor integrates a Neural Processing Unit (NPU).
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  Per Vognsen (pervognsen@mastodon.social)'s status on Tuesday, 05-Aug-2025 08:29:36 JST Per Vognsen
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  - Fabian Giesen
  @whitequark I think it disappeared when we all deleted our Twitter accounts but there I remember a thread with me and @rygorous with "Imagine having 'Did bring-up for OpenVMS on Kittson [the last gen of Itanium] on your resume" after we saw a particularly cursed thing.
  
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  ✧✦Catherine✦✧ (whitequark@mastodon.social)'s status on Tuesday, 05-Aug-2025 10:13:12 JST ✧✦Catherine✦✧
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  @rygorous @chrisvest I think Synopsys offered ARC for a while as licensable IP so it's in a lot of places where you'd want something more powerful than a 8051 especially if you want DSP
  looks like they still offer an ARC lineup but for some insane marketing reason it now includes RISC-V cores
  
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  ✧✦Catherine✦✧ (whitequark@mastodon.social)'s status on Tuesday, 05-Aug-2025 10:13:13 JST ✧✦Catherine✦✧
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  @rygorous @chrisvest ARC is pretty widely used to this day, it's not (just) a weird macro someone at Intel picked for that GPU, but is used by other devices and vendors too; some examples include Thunderbolt silicon (as far as I could tell) and MEC16xx (i wrote an in-circuit programmer for that)
  
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  Fabian Giesen (rygorous@mastodon.gamedev.place)'s status on Tuesday, 05-Aug-2025 10:13:14 JST Fabian Giesen
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  @chrisvest @whitequark honestly something derived from an actual normal ISA you've heard of sounds positively sane, these random microcontrollers have a long and proud history of running the most obscure stuff imaginable because usually someone picked whatever was cheap out of a bin 25 years ago.
  E.g. Intel's Management Engine firmware used (long ago) to run on ARC cores https://en.wikipedia.org/wiki/ARC_(processor) - literally derived from the SNES SuperFX chip. Not making this up.
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    ARC (processor)
    
    Argonaut RISC Core (ARC) is a family of 32-bit and 64-bit reduced instruction set computer (RISC) central processing units (CPUs) originally designed by ARC International. ARC processors are configurable and extensible for a wide range of uses in system on a chip (SoC) devices, including storage, digital home, mobile, automotive, and Internet of things (IoT) applications. They have been licensed by more than 200 organizations and are shipped in more than 1.5 billion products per year. ARC processors employ the 16-/32-bit ARCompact compressed instruction set instruction set architecture (ISA) that provides good performance and code density for embedded and host SoC applications. History The ARC concept was developed initially within Argonaut Games through a series of 3D pipeline development projects starting with the Super FX chip for the Super Nintendo Entertainment System. In 1995, Argonaut was split into Argonaut Technologies Limited (ATL), which had a variety of technology projects, and Argonaut Software Limited (ASL). At the start of 1996, the General Manager of...
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  Fabian Giesen (rygorous@mastodon.gamedev.place)'s status on Tuesday, 05-Aug-2025 10:13:15 JST Fabian Giesen
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  @chrisvest @whitequark Something needs to parse your command buffers, handle scheduling, initiate interrupts and deal with other plumbing etc., and it's not going to be your matrix multiply unit.
  For the AMD GPU equivalent, https://gpuopen.com/download/micro_engine_scheduler.pdf "The GPU frontend has three micro-processors meant to execute scheduling, compute
  and gfx firmware".
  It's the things that run the infamous GPU Mystery Firmware Blobs™.
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  Fabian Giesen (rygorous@mastodon.gamedev.place)'s status on Tuesday, 05-Aug-2025 10:13:16 JST Fabian Giesen
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  @chrisvest @whitequark it's not an array of SPARC processors, it's a bunch of actual NPU and DSP tiles each with a SPARC-derived microcontroller as its frontend - same way that say GPUs usually have some random microcontroller concoction as part of their command processing frontend, but that's not what's doing the math
  
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  Per Vognsen (pervognsen@mastodon.social)'s status on Tuesday, 05-Aug-2025 10:23:29 JST Per Vognsen
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  @whitequark @rygorous @chrisvest Xtensa too. Since the core ISA never seemed to be the main selling point (although Xtensa had some interesting ideas like a newer take on register windows and 24-bit RISC instructions) and if anything was a detriment insofar as they're relatively niche when it comes to the software ecosystem, I'm not surprised RISC-V is taking over there.
  
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  ✧✦Catherine✦✧ (whitequark@mastodon.social)'s status on Tuesday, 05-Aug-2025 10:29:08 JST ✧✦Catherine✦✧
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  @pervognsen @rygorous @chrisvest yeah, RV is basically the Unix of ISAs
  
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  Per Vognsen (pervognsen@mastodon.social)'s status on Tuesday, 05-Aug-2025 10:41:43 JST Per Vognsen
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  @whitequark @rygorous @chrisvest This also reminded me that Xilinx had their own truly awful DLX-inspired ISA for MicroBlaze but it looks like the newer MicroBlaze cores are RISC-V as well: https://en.wikipedia.org/wiki/MicroBlaze
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    MicroBlaze
    
    The MicroBlaze is a soft microprocessor core designed for Xilinx field-programmable gate arrays (FPGA). As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs. MicroBlaze was introduced in 2002. Overview In terms of its instruction set architecture, MicroBlaze is similar to the RISC-based DLX architecture described in a popular computer architecture book by Patterson and Hennessy. With few exceptions, the MicroBlaze can issue a new instruction every cycle, maintaining single-cycle throughput under most circumstances. The MicroBlaze has a versatile interconnect system to support a variety of embedded applications. MicroBlaze's primary I/O bus, the AXI interconnect, is a system-memory mapped transaction bus with master–slave capability. Older versions of the MicroBlaze used the CoreConnect PLB bus. The majority of vendor-supplied and third-party IP interface to AXI directly (or through an AXI interconnect). For access to local-memory (FPGA RAM), MicroBlaze uses a dedicated LMB bus, which provides fast on-chip storage. User-defined coprocessors are...

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