Notices by TheZoq2 (thezoq2@mastodon.social), page 2

@wren6991 The only piece missing from that puzzle at this point is a good verilator wasm port. (There is one but it is several years old and has a few annoying limitations, like not allowing >64 bit signals iirc)

After *checks notes* 8 months, I finally got around to doing another Surfer release 🎉

The change log is long with lots of big and small changes, my favorites being the new wasm based translators, and improvements to the waveform control protocol.

I also took the opportunity to set up automatic builds of the VSCode extension from `main` so it will be in sync with the rest of our binaries :)

Full change log at https://gitlab.com/surfer-project/surfer/-/blob/main/CHANGELOG.md?ref_type=heads#040---2025-11-06

#fpga #asic #verilog #vhdl

@whitequark @multisn8 I too want to know what this abomination is

@whitequark Oh yeah, quickscope is like 100 lines of HDL and 200 lines of client code. Probably much better to re-implement something similar in Amaranth :D

A Surfer plugin for Amaranth would be super cool. My goal from the start was to have more HDLs do rich translation with it but I only added the wasm system for that recently

@whitequark If you want to copy that system, you'll have to implement a Surfer plugin for Amaranth types (can be used for both Sim and this) https://docs.surfer-project.org/translator_docs/index.html

You could also do the unwrapping when generating the vcd file too, I just did it this way because I already have the Surfer translation infrastructure in place

@whitequark Shouldn't be that hard, it is essentially 3 parts

Quickscope itself that runs on the hardware, it just serializes an arbitrary value https://gitlab.com/TheZoq2/quickscope

The client (./client) does reads the serialized data from the serial port (main.rs), and for the Spade integration, works out which which top module was used for the quickscope instantiation (spade.rs). It then writes the .vcd file -> top module mapping which the Spade plugin for Surfer looks for https://gitlab.com/spade-lang/spade/-/tree/main/spade-surfer-plugin?ref_type=heads

Here it is in use, with newly added Surfer integration so it shows actual Spade values instead of just bit vectors :)

Integrated logic analyzer in Spade that perfectly fits in a mastodon alt-text and took about 3 hours to write :)

You just hook the output up to anything that can consume an `Rv<uint<8>>`. For example a UART driver or UDP streamer

(I think it works at least, my one test case does do the right thing but I haven't tried it in hardware on account of it being 10pm)

@whitequark @mei @0xabad1dea journal of advanced research sure sounds like a paper mill publication, and I guess the title of the paper as well

@whitequark It certainly doesn't make either "language" look good :D

I have been writing react the bast few days, and I can't shake the feeling that react has the same fundamental programming model as VHDL and Verilog

You have a bunch of state, and any you update that state with ~~processes~~ effects, which are triggered by changes to other state

@multisn8 @whitequark I think DDG has a toggle to never show AI summaries

And just like that I have now successfully defended my PhD :)

@whitequark oh yeah, I'm looking forward to that

Challenge: Write Spade for an hour without nerd sniping myself into writing more tooling [Impossible]

This time, I didn't like the readability of nextpnr timing reports

This is actually a pretty exciting commit. I've finally added a WASM based plugin system to Surfer, so the Spade integration can now live in its own repo and be loaded at runtime

No more having to have a surfer version that matches the Spade version you're using!

There it is!

My thesis is now published online :blobcat:

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-214272

@whitequark Ah yes, verilog concatenation syntax, truly the most universal way to express this

Also, beautiful formatting, no notes

On March 30, we're hosting LATTE ☕ - A Workshop on Languages, Tools, and Techniques for Accelerator Design at ASPLOS

If you're working with languages and/or accelerators, you should absolutely submit a paper! The focus of the workshop is discussion, so papers on work in progress ideas and projects, or papers that identify gaps that need to be solved are highly encouraged!

Papers are 2 pages and the deadline for submission is on January 31

More info at https://capra.cs.cornell.edu/latte25/