Notices by Andrew Zonenberg (azonenberg@ioc.exchange)

@0xabad1dea makes perfect sense to me. they SHA256 your message with a random salt over and over until it starts with a specified number of zeroes.

Then they encrypt it with a completely unrelated key, send a copy to Palantir and the Chinese communist party, and wait for the VC dollars to roll in.

Don't mind me, just over here escape-routing this BGA inside out

It made the connector routing so much easier. Otherwise I'd have to swizzle lanes in all kinds of awkward ways with lots of mid-span vias and criscrossing. It's much cleaner this way.

@whitequark only rgmii but yes its divided rate at low speed

@whitequark @sycophantic My own implementation looks for I think at least one 55 as a state machine trigger followed by a D5 and then goes to frame content. Do not count the 55s, some PHYs/protocols can remove some of them (e.g. 10baseT before bit sync is achieved)

@whitequark yes, 64 octets including src/dest MAC, 802.1q tag if present, ethertype/length, frame body, and FCS.

Preamble/SFD and interframe gap do not count towards the 64

@sycophantic @whitequark Interesting all of my MACs to date has just treated the 802.1q tag the same as an ethertype for the most part (only caring about the tag once i start making forwarding decisions) and my padding insertion logic pads the entire frame to 64.

I haven't got to the point of adding outbound 802.1q tags on trunk ports yet but when I do, I'll probably need to patch my MAC code that does padding insertion to change the target frame length based on whether a tag is present

@whitequark @unlambda Ah, OK.

I have the opposite (replay pcapng as frames over axi4-stream) for switch fabric debugging but currently no pcap sink

@whitequark @unlambda (yes i implemented a pcapng parser in systemverilog, call me crazy but i'd rather do that than use python)

@whitequark @unlambda Wow.

Honestly I didn't even know it was possible to get FCSes in Wireshark because NICs normally drop frames with bad FCS so they don't show up in the capture.

Any time I've needed to troubleshoot FCS stuff I've slapped scope probes down on the *MII bus or the SFP diff pair or used my SFP/RJ45 mid-span tap fixtures then decoded in ngscopeclient

@whitequark sorry now you can't unsee lol

@whitequark i'm really curious what the thought process was... MMD extended registers existed alrerady, there was no reason to roll their own indirect accessing scheme.

except maybe performance, if you bank then accessing any register in the range is faster than making repeated address + data accesses? but what kind of system gets bottlenecked on mdio bandwidth

@whitequark I use the term MDIO for the bus in all of my usage

@whitequark More generally, do you have any plans to cleanly support nonstandard register banking schemes as used in e.g. the VSC8512?

(tl;dr MDIO register 31 is used as a bank selector to determine which page of extended registers 16-30 map to, 0-15 are always the IEEE standard ones. it's derpy and I dont know why they didn't juse MMD extended registers)

@dalias s/mod/politician/ and the same applies

@dalias more generally anyone seeking out a position of power over others is probably the last person you should trust to actually wield such power

@whitequark Do you need an ANTISTATISKHAJ too? Lol

My kingdom for a datasheet where all of the coordinates in the mechanical drawings are referenced to a single datum. I don't care if it's the center or a corner or what.

Anything but... this.

I'm getting increasingly fed up with making SPI peripherals in software because you have unnecessarily tight hard realtime constraints to make the protocol work (if you don't respond within the set time the other side reads garbage).

In gateware you can easily enforce cycle accurate timing and on the host side the timing isn't critical.

Thinking about switching my supervisor MCUs to use i2c instead of spi for interfacing to the main CPU.

Rationale: uses two less pins, can be combined with sensors and other system health stuff on 3v3_sb power domain, simpler code with no hard realtime constraints since you can clock stretch if the other side isn't ready, and it doesn't need to be fast at all.