@p @dj @ryan @phnt @ins0mniak @lanodan RISC-V is merely an instruction set reference with some sample hardware designs, which really need to be shoved into a SoC and then manufactured if you want to use them.

Just because an instruction set is documented doesn't mean that the init required for the SoC won't be absolutely proprietary and require reverse engineering.

All fast RISC-V SoC's I've looked at (i.e. with DDR4) use proprietary software for RAMinit.