The FPGA for the VERA is only very slightly different from the X16's implementation. It was more efficient on hardware to make the VERA IRQ output active-high, since I had an extra active-high interrupt line in the CPU to use up.
The FPGA for the VERA is only very slightly different from the X16's implementation. It was more efficient on hardware to make the VERA IRQ output active-high, since I had an extra active-high interrupt line in the CPU to use up.
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