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   Studio 8502 :verified: (mos_8502@soc.studio8502.ca)'s status on Sunday, 17-Dec-2023 10:36:17 JST Studio 8502 :verified:

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   The FPGA for the VERA is only very slightly different from the X16's implementation. It was more efficient on hardware to make the VERA IRQ output active-high, since I had an extra active-high interrupt line in the CPU to use up.