William D. Jones
#lazyweb Is it correct to say that the 68000 and 68008 only have atomic load/stores of 16-bit and 8-bits respectively*?
* Unlike most CPUs, an interrupt will pause the current instruction and continue from where it left off. But I haven't read the patent or RE'd microcode. So not clear to me if 68000 will wait to honor an interrupt until after an up-to-32-bit load/store completes.
Rich Felker
@cr1901 Interrupts generally only happen at whole instruction boundaries. Otherwise resuming after the interrupt returns would not work, since the saved PC can't be at some magical halfway place between instructions.
William D. Jones
@dalias This is correct for most CPUs; the 68k saves enough of its internal state to the stack on interrupt to continue in the middle of an instruction. It's in the patent, supposedly*.
* Which, I did not read, and I've heard conflicting info over the years as to whether the patent correctly describes all the saved state.
Rich Felker
@cr1901 I'm familiar with "68k" as the mmu-ful models 68020 (I think I got that right) and up, which almost certainly don't do this because it's a behavior not very compatible with a multitasking privilege-domain-separated operating system. It can be made to work, but it's not pretty, and I never noticed any Linux code to work around that.
If you do have to deal with it on mmu-less, the reasonable thing to do would probably be to insert a breakpoint instruction at the next instruction boundary and immediately return from the interrupt. This would give you atomicity at instruction granularity whenever your interrupt handling code's body actually runs.
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