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#lazyweb Is it correct to say that the 68000 and 68008 only have atomic load/stores of 16-bit and 8-bits respectively*?

* Unlike most CPUs, an interrupt will pause the current instruction and continue from where it left off. But I haven't read the patent or RE'd microcode. So not clear to me if 68000 will wait to honor an interrupt until after an up-to-32-bit load/store completes.