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   clacke (clacke@libranet.de)'s status on Sunday, 03-Sep-2023 03:41:50 JST clacke

   • Csepp ?

   @csepp Fascinating! I've been wondering what default emulated ISA would emerge.

   The science fiction slice of life "Programmer at Large" predicted that our interstellar ships would be running obscure sewage pump and greenhouse control code on x86 emulation. I've been thinking maybe everything will be WASM, CLR or JVM before we reach the stars, or something made specifically for the purpose (if one would argue that those three aren't).

   I wasn't expecting RISC-V, and especially not this soon.

   • Embed this notice
     Jens Finkhäuser (jens@social.finkhaeuser.de)'s status on Sunday, 03-Sep-2023 03:42:28 JST Jens Finkhäuser

     in reply to

     • Csepp ?

     @clacke @csepp Why not MMIX?

     https://en.m.wikipedia.org/wiki/MMIX

     clacke likes this.
   • Embed this notice
     clacke (clacke@libranet.de)'s status on Sunday, 03-Sep-2023 03:42:29 JST clacke

     in reply to

     • Csepp ?
     • Jens Finkhäuser

     @jens @csepp Sure, why not? (I'm sure lots of people out there could tell us why not, regardless if they have a better suggestion)

     Or why not MIPS? I thought for a while that that the VM target of the future might be the non-patent-encumbered subset of MIPS. RISC-V makes more sense at this point.

     Or Parrot VM bytecode? I'm thinking that if it's a deliberate decision for the longevity of compiled code, a physical CPU architecture is probably not the right format. LLVM IR has been mentioned here in the thread, that might be good if the spec is stable.

     But it probably won't be deliberate but emergent, and in that case I'm assuming we're better off with RISC-V than with x86.