Graham Sutherland / Polynomial@manawyrm @ryanc holding the CPU in reset would not necessarily put the SPI IOs in a hi-Z state though, and I have seen folks kill boards by trying to assert CS and essentially dead-shorting the low-side output FET on the MCU's GPIO across the rails. with sufficient resistance you can avoid that but it requires calculating the necessary value based on the max sink current rating for the chip, and then you have to think about IO thresholds with any existing pull-ups/pull-downs... it gets messy.
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