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<blockquote style="position: relative; padding-left: 55px;"><section><a href="https://rollenspiel.social/users/ArneBab/statuses/113870722331536356">Arne Babenhauserheide (arnebab@rollenspiel.social)'s status on Wednesday, 22-Jan-2025 16:02:15 JST</a><a href="https://rollenspiel.social/@ArneBab" title="arnebab@rollenspiel.social"><img src="https://gnusocial.jp/avatar/8121-48-20230128222518.webp" width="48" height="48" alt="Arne Babenhauserheide" style="position: absolute; left: 0; top: 0;">Arne Babenhauserheide</a><div><ul><li></ul></div></section><article><p><a href="https://ohai.social/@dcoderlt">@dcoderlt</a> missing here: how did *latency* of hardware improve?</p><p>I’m asking because latency — not throughput — is what we feel when we interact with a computer, and negating the latency improvements is far easier than negating the throughput improvements.</p><p>See for example access memory times not getting much faster:<br><a href="https://en.wikipedia.org/wiki/CAS_latency#Memory_timing_examples" rel="nofollow noreferrer">https://en.wikipedia.org/wiki/CAS_latency#Memory_timing_examples</a></p><p>(though L1 cache did, but you’re fare away of that if you have to react to keyboard input)</p></article><footer><a rel="bookmark" href="https://gnusocial.jp/conversation/4423054#notice-8652670">In conversation</a><time datetime="2025-01-22T16:02:15+09:00" title="Wednesday, 22-Jan-2025 16:02:15 JST">about 9 months ago</time> <span>from <span><a href="https://rollenspiel.social/@ArneBab/113870722331536356" rel="external" title="Sent from rollenspiel.social via ActivityPub">rollenspiel.social</a></span></span><a href="https://rollenspiel.social/@ArneBab/113870722331536356">permalink</a><h4>Attachments</h4><ol><li><article><header><div>No result found on File_thumbnail lookup.</div><h5><a href="https://en.wikipedia.org/wiki/CAS_latency#Memory_timing_examples(though">CAS latency</a></h5><div></div></header><div>Column address strobe latency, also called CAS latency or CL, is the delay in clock cycles between the READ command and the moment data is available. In asynchronous DRAM, the interval is specified in nanoseconds (absolute time).  In synchronous DRAM, the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of absolute time, the actual time for an SDRAM module to respond to a CAS event might vary between uses of the same module if the clock rate differs.RAM operation backgroundDynamic RAM is arranged in a rectangular array.  Each row is selected by a horizontal word line. Sending a logical high signal along a given row enables the MOSFETs present in that row, connecting each storage capacitor to its corresponding vertical bit line.  Each bit line is connected to a sense amplifier that amplifies the small voltage change produced by the storage capacitor. This amplified signal is then output from the DRAM chip as well as driven back up the bit line to refresh the row.
When no word line is active, the array is...</div><footer></footer></article></li></ol></footer></blockquote>

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Arne Babenhauserheide (arnebab@rollenspiel.social)'s status on Wednesday, 22-Jan-2025 16:02:15 JSTArne Babenhauserheide
- DCoder 🇱🇹❤🇺🇦
@dcoderlt missing here: how did *latency* of hardware improve?
I’m asking because latency — not throughput — is what we feel when we interact with a computer, and negating the latency improvements is far easier than negating the throughput improvements.
See for example access memory times not getting much faster:
https://en.wikipedia.org/wiki/CAS_latency#Memory_timing_examples
(though L1 cache did, but you’re fare away of that if you have to react to keyboard input)
In conversationabout 9 months ago from rollenspiel.socialpermalink
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  CAS latency
  Column address strobe latency, also called CAS latency or CL, is the delay in clock cycles between the READ command and the moment data is available. In asynchronous DRAM, the interval is specified in nanoseconds (absolute time). In synchronous DRAM, the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of absolute time, the actual time for an SDRAM module to respond to a CAS event might vary between uses of the same module if the clock rate differs. RAM operation background Dynamic RAM is arranged in a rectangular array. Each row is selected by a horizontal word line. Sending a logical high signal along a given row enables the MOSFETs present in that row, connecting each storage capacitor to its corresponding vertical bit line. Each bit line is connected to a sense amplifier that amplifies the small voltage change produced by the storage capacitor. This amplified signal is then output from the DRAM chip as well as driven back up the bit line to refresh the row. When no word line is active, the array is...

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