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@Burger@dill.burggit.moe @apropos@fsebugoutzone.org

If my understanding of AI's explanation is correct - and there's two possible points of failure here - the CPU sockets (some of them) are basically wired directly to the memory controller, and the memory controller is wired directly to the memory slots, plus whatever other I/O the memory controller supports.

The CPU is also wired directly to a chip that is the "northbridge" ( like an Ethernet switch for high-speed internal peripheral connections, using a standard like PCI) and another one that is the "southbridge" (for external peripherals like USB).

USB sockets can be placed on the same PCB tracelead or conductive medium; the client devices wait patiently for the USB controller (sourthbridge) to give them their assigned turn.

Same is true for northbridge and PCI.

The data connections from CPU to memory controller, CPU to northbridge, and CPU to southbridge are unmediated point-to-point connections, with nothing but low-impedance conductive metal between them.