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<blockquote style="position: relative; padding-left: 55px;"><section><a href="https://queer.hacktivis.me/objects/7814f2f1-db6b-48af-96d8-f9b4843aaa9b">Haelwenn /элвэн/ :triskell: (lanodan@queer.hacktivis.me)'s status on Tuesday, 07-Jan-2025 18:35:34 JST</a><a href="https://queer.hacktivis.me/users/lanodan" title="lanodan@queer.hacktivis.me"><img src="https://gnusocial.jp/avatar/792-48-20230912093141.webp" width="48" height="48" alt="Haelwenn /элвэн/ :triskell:" style="position: absolute; left: 0; top: 0;">Haelwenn /элвэн/ :triskell:</a><div><a href="https://piggo.space/objects/f3d8a3f9-8c91-4f7b-8f6a-1a3e6edb54d2" rel="in-reply-to">in reply to</a><ul><li><li><a href="https://gnusocial.jp/user/21761" title="eragon@pl.eragon.re">Eragon</a></li></ul></div></section><article><a href="https://piggo.space/users/piggo">@piggo</a> <a href="https://hai.z0ne.social/@kura">@kura</a> <a href="https://pl.eragon.re/users/eragon">@eragon</a> riscv isn't just an ISA though, like boot and device discovery is standardized: <a href="https://github.com/riscv-non-isa/riscv-brs">https://github.com/riscv-non-isa/riscv-brs</a><br><br>Meanwhile yeah, arm is the one that frequently is just a lonely CPU on a board with no boot chip.</article><footer><a rel="bookmark" href="https://gnusocial.jp/conversation/4326772#notice-8459286">In conversation</a><time datetime="2025-01-07T18:35:34+09:00" title="Tuesday, 07-Jan-2025 18:35:34 JST">about 4 months ago</time> <span>from <span><a href="https://queer.hacktivis.me/objects/7814f2f1-db6b-48af-96d8-f9b4843aaa9b" rel="external" title="Sent from queer.hacktivis.me via ActivityPub">queer.hacktivis.me</a></span></span><a href="https://queer.hacktivis.me/objects/7814f2f1-db6b-48af-96d8-f9b4843aaa9b">permalink</a><h4>Attachments</h4><ol><li><article><header><div>Domain not in remote thumbnail source whitelist: opengraph.githubassets.com</div><h5><a href="https://github.com/riscv-non-isa/riscv-brs">GitHub - riscv-non-isa/riscv-brs: The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.</a></h5><div></div></header><div>The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectation...</div><footer></footer></article></li></ol></footer></blockquote>

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Haelwenn /элвэн/ :triskell: (lanodan@queer.hacktivis.me)'s status on Tuesday, 07-Jan-2025 18:35:34 JSTHaelwenn /элвэн/ :triskell:
in reply to
- Piggo :verified_horse:
- Eragon
@piggo @kura @eragon riscv isn't just an ISA though, like boot and device discovery is standardized: https://github.com/riscv-non-isa/riscv-brs

Meanwhile yeah, arm is the one that frequently is just a lonely CPU on a board with no boot chip.
In conversationabout 4 months ago from queer.hacktivis.mepermalink
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1. Domain not in remote thumbnail source whitelist: opengraph.githubassets.com
  GitHub - riscv-non-isa/riscv-brs: The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.
  The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectation...

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