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<blockquote style="position: relative; padding-left: 55px;"><section><a href="https://social.shadowkat.net/objects/bd454316-ad33-4aae-b643-7f7d540f9f60">Xeon² (izaya@social.shadowkat.net)'s status on Saturday, 06-Apr-2024 17:50:10 JST</a><a href="https://social.shadowkat.net/users/izaya" title="izaya@social.shadowkat.net"><img src="https://gnusocial.jp/avatar/3966-48-20220808121910.webp" width="48" height="48" alt="Xeon²" style="position: absolute; left: 0; top: 0;">Xeon²</a><div><a href="https://queer.hacktivis.me/objects/78c66e47-9572-454c-923f-12d6ed3e2a31" rel="in-reply-to">in reply to</a><ul><li></ul></div></section><article><a href="https://queer.hacktivis.me/users/lanodan">@lanodan</a> there is! but I know the chipsets always implement two ports, and there's only one header!</article><footer><a rel="bookmark" href="https://gnusocial.jp/conversation/2904653#notice-5776457">In conversation</a><time datetime="2024-04-06T17:50:10+09:00" title="Saturday, 06-Apr-2024 17:50:10 JST">about 8 months ago</time> <span>from <span><a href="https://social.shadowkat.net/objects/bd454316-ad33-4aae-b643-7f7d540f9f60" rel="external" title="Sent from social.shadowkat.net via ActivityPub">social.shadowkat.net</a></span></span><a href="https://social.shadowkat.net/objects/bd454316-ad33-4aae-b643-7f7d540f9f60">permalink</a></footer></blockquote>

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Xeon² (izaya@social.shadowkat.net)'s status on Saturday, 06-Apr-2024 17:50:10 JSTXeon²
in reply to
- Haelwenn /элвэн/ :triskell:
@lanodan there is! but I know the chipsets always implement two ports, and there's only one header!
In conversationabout 8 months ago from social.shadowkat.netpermalink

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