@FailurePersonified

> A fair objection; up until about a few months ago that was my thoughts almost exactly.

It is rare that I am this pleased to be proven wrong.

> I've read a lot about some peeps experiences and it's hard to really figure if it's just a "them problem" or something deeper.

The only bad things I have heard about it are people being disappointed that this specific chip is underpowered. If anyone is having a bad time with it, that's news to me.

> Main line software is only going to get more bloated,

That can't hold up. The plan is to make it computationally infeasible to run your own infra.

> The vector processing is such a cool idea, but I understand why, especially back during it's time; it was a bit too forward thinking.

:cray:

> One of the big reasons ASICs are so big in mining, from my understanding, is a closer relationship between what's being requested, and an optimized path for those instructions

Well, if you don't have to have something that's generally programmable and it's got one task, then you don't have to fetch instructions from memory, decode them, pipeline them, catch an interrupt from the SATA controller, wait for the memory bus.

> He's right; however I can't help but get a little hopeful :02_laugh:

He's almost always right. :linus:

In general, the cautious perspective is almost always right and all advances happen during rare moments when it's completely wrong.

> I hope that people will be more open to RISC-V once it matures a bit more.

Right now, while it's new but things are working, this is where the opportunity is.