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<blockquote style="position: relative; padding-left: 55px;"><section><a href="https://libranet.de/objects/0b6b25a8-1565-42e7-898f-b51858916894">clacke (clacke@libranet.de)'s status on Thursday, 02-Nov-2023 09:29:32 JST</a><a href="https://libranet.de/profile/clacke" title="clacke@libranet.de"><img src="https://gnusocial.jp/theme/gnusocialjp/default-avatar-stream.png" width="48" height="48" alt="clacke" style="position: absolute; left: 0; top: 0;">clacke</a><div><a href="https://c.im/@TimWardCam/111337940588427622" rel="in-reply-to">in reply to</a><ul><li><li><a href="https://gnusocial.jp/user/117916" title="f4grx@chaos.social">F4GRX SÃ©bastien</a></li><li><a href="https://gnusocial.jp/user/171938" title="drj@typo.social">David JONES</a></li></ul></div></section><article>&gt; In <a href="https://developer.ibm.com/articles/pa-dalign/" rel="noreferrer">this IBM article</a> from 2005, it is covered how the Motorola m68k, MIPS and PowerPC CPUs of that era handled unaligned access. The interesting thing to note here is that until the 68020, unaligned access would always throw a bus error. MIPS CPUs didn’t bother with unaligned access in the name of speed, and PowerPC took a hybrid approach, with 32-bit unaligned access allowed, but 64-bit (floating point) unaligned access resulting a bus error.<p><br><a href="https://hackaday.com/2022/05/10/data-alignment-across-architectures-the-good-the-bad-and-the-ugly/" rel="noreferrer">hackaday.com/2022/05/10/data-a…</a></p><p><a href="https://c.im/users/TimWardCam">@TimWardCam</a> <a href="https://chaos.social/users/f4grx">@f4grx</a> <a href="https://typo.social/users/drj">@drj</a></p></article><footer><a rel="bookmark" href="https://gnusocial.jp/conversation/2266298#notice-4466972">In conversation</a><time datetime="2023-11-02T09:29:32+09:00" title="Thursday, 02-Nov-2023 09:29:32 JST">Thursday, 02-Nov-2023 09:29:32 JST</time> <span>from <span><a href="https://libranet.de/display/0b6b25a8-1565-42e7-898f-b51858916894" rel="external" title="Sent from libranet.de via ActivityPub">libranet.de</a></span></span><a href="https://libranet.de/display/0b6b25a8-1565-42e7-898f-b51858916894">permalink</a><h4>Attachments</h4><ol><li><article><header><div>Domain not in remote thumbnail source whitelist: hackaday.com</div><h5><a href="https://hackaday.com/2022/05/10/data-alignment-across-architectures-the-good-the-bad-and-the-ugly/">Data Alignment Across Architectures: The Good, The Bad And The Ugly</a></h5><div> from <span>Maya Posch</span></div></header><div>Even though a computer’s memory map looks pretty smooth and very much byte-addressable at first glance, the same memory on a hardware level is a lot more bumpy. An essential term a developer …</div><footer></footer></article></li></ol></footer></blockquote>

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clacke (clacke@libranet.de)'s status on Thursday, 02-Nov-2023 09:29:32 JSTclacke
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> In this IBM article from 2005, it is covered how the Motorola m68k, MIPS and PowerPC CPUs of that era handled unaligned access. The interesting thing to note here is that until the 68020, unaligned access would always throw a bus error. MIPS CPUs didn’t bother with unaligned access in the name of speed, and PowerPC took a hybrid approach, with 32-bit unaligned access allowed, but 64-bit (floating point) unaligned access resulting a bus error.

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In conversationThursday, 02-Nov-2023 09:29:32 JST from libranet.depermalink
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  Data Alignment Across Architectures: The Good, The Bad And The Ugly
  from Maya Posch
  Even though a computer’s memory map looks pretty smooth and very much byte-addressable at first glance, the same memory on a hardware level is a lot more bumpy. An essential term a developer …

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