Darrell Harmon@azonenberg The Xilinx documented way of using Zynq is indeed a pain. I've done direct instantiation of the PS block (Zynq-7), a small TCL script that generates an IP core breaking out all the desired AXI busses for the more complex Zynq US+. Configuration and startup is ugly the Xilinx way too. I've worked around that and have an open source CLI flow.
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