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@pervognsen What struck me when I looked at modern attempts to Verilog/VHDL is that for many, their code read not like I was programming what the hardware would look like, but like I was writing a program that would assemble the hardware. E.g., you have to "make_signal" instead of just having the signal as part of the language.

It's a subtle distinction, and I'm now a HW person, but it felt really odd to me because SW languages don't work that way. We don't say "make_loop", we say "for".