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   Per Vognsen (pervognsen@mastodon.social)'s status on Tuesday, 01-Jul-2025 03:56:40 JST Per Vognsen

   Revisiting some of my old Rattle HDL design ideas for Python (with a Rust-based core) with an eye towards seeing how much you can make things work with a statically type checkable facade while doing metaprogramming behind the static type checker's back. This statically type checks with pyright: https://gist.github.com/pervognsen/fc6a19d6c021f49826beea0c8840cc53

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     Alfred M. Szmidt (amszmidt@mastodon.social)'s status on Tuesday, 01-Jul-2025 03:56:38 JST Alfred M. Szmidt

     in reply to

     • Nicolai Hähnle

     @nh @pervognsen Why not just .. use VHDL? It is quite OK, even modern versions for HDL.

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     Nicolai Hähnle (nh@mastodon.gamedev.place)'s status on Tuesday, 01-Jul-2025 03:56:40 JST Nicolai Hähnle

     in reply to

     @pervognsen What struck me when I looked at modern attempts to Verilog/VHDL is that for many, their code read not like I was programming what the hardware would look like, but like I was writing a program that would assemble the hardware. E.g., you have to "make_signal" instead of just having the signal as part of the language.

     It's a subtle distinction, and I'm now a HW person, but it felt really odd to me because SW languages don't work that way. We don't say "make_loop", we say "for".