Conversation

Notices

1. Embed this notice
   sodiboo (sodiboo@gaysex.cloud)'s status on Sunday, 04-May-2025 06:06:07 JST sodiboo

   in reply to

   • Julia :v_trans: :v_bi: (not cute)

   @julia@eepy.moe modern CPUs are literally just a hardware-accelerated JIT compiler with a memory-unsafe bytecode. branch prediction can and will assume things about your code that Isn't Always True and execute it as if it were (because that's faster), and that takes a huge performance hit when you *don't* meet that assumption (just like how in javascript if you suddenly pass a different type of arg, that call will be slower)
   
   this is also why they come with so many side chain attacks and need security patches (microcode). it's a huge complex optimizing system and it's thanks to some FUCKING AWSOME and WILDLY IMPRESSIVE engineering efforts.

   • Jesse 🇫🇷 likes this.
   • Embed this notice
     sodiboo (sodiboo@gaysex.cloud)'s status on Sunday, 04-May-2025 06:06:08 JST sodiboo

     in reply to

     • Julia :v_trans: :v_bi: (not cute)

     @julia@eepy.moe like they'll reorder your instructions too. as long as you can't tell the difference between the result, anything goes. afaik on modern x86, if you make multiple independent calculations on a single register but overwrite it in-between, the CPU can and will realize they are independent, assign those instructions physically disjoint registers, and happily execute that shit out of order whilst waiting for a memory access that doesn't affect the results.
     
     this is also, I believe (warning: hallucation) part of the reason why you have to be strict about multithreading and atomic access. because if you don't tell the CPU exactly how to coordinate this, then like. lol, lmao. good luck.

   • Embed this notice
     sodiboo (sodiboo@gaysex.cloud)'s status on Sunday, 04-May-2025 06:06:10 JST sodiboo

     • Julia :v_trans: :v_bi: (not cute)

     @julia@eepy.moe isn't this just. a CPU. pretty sure modern CPUs do this (as long as the proceeding instructions aren't literally dependent on the result of this memory access)