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:umu: :umu: (a1ba@suya.place)'s status on Friday, 21-Mar-2025 00:46:45 JST :umu: :umu:
@koakuma I don't know a lot about their SPARC processors, some of the information must be available in the [book](http://www.mcst.ru/doc/book_121130.pdf), half of it is literally about their SPARCs, but it's older R500 and R1000, I suppose they should be somewhat close to UltraSparc III.
Their current SPARC CPU is R2000+, which according to binutils source also borrows and adds unique instructions...- Haelwenn /элвэн/ :triskell: likes this.
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Sun Microdevil Pte Ltd (koakuma@uwu.social)'s status on Friday, 21-Mar-2025 00:46:46 JST Sun Microdevil Pte Ltd
@a1ba Huh, funny that they actually implemented all the VIS extensions but skipped the UA/OSA ones (particularly, no hardware cryptography!)
Also,
> +/* This is an MCST specific version of store. Hopefully, it hasn't been
> + implemented anywhere else in this file since binutils-2.18 . . . */
> +{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(0x30), "H,2,[1]A", 0, 0, 0, v9 }, /* stda d,rs2, [rs1] */I wonder if this is a 128-bit atomic store? VIS2 already specifies a 128-bit atomic load instruction so it makes sense to provide the counterpart.
Though on the other hand the lack of 128-bit atomic CAS is very odd, given that - unless you're playing weird games with your page permissions - most, if not all stores can be emulated with a CAS.
(Though this applies too to Sun's rather weird decision here lol) -
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:umu: :umu: (a1ba@suya.place)'s status on Friday, 21-Mar-2025 00:46:47 JST :umu: :umu:
some of their sparc extensions here too cc @koakuma -
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:umu: :umu: (a1ba@suya.place)'s status on Friday, 21-Mar-2025 00:46:48 JST :umu: :umu:
mcst published newer binutils 2.41 with elbrus-v7 stuff.
I rebased the sources on top of upstream binutils git repo: https://github.com/OpenE2K/binutils-gdb/commit/f6dcf84f4a6e2f8689c575957ab59e7cf41c93e0