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   alcinnz (alcinnz@floss.social)'s status on Tuesday, 14-Jan-2025 04:37:02 JST alcinnz

   In planning a future "graphics workstation" hypothetical, after having looked over Blender's dependencies I'm quite settled on the hardware I'd want for it.

   In mid-20'00s terms... PS3-style "Synergistic Porcessing Units" with a XBox360-style GPU (which basically any GPU now) coordinated by (for the sake of it) a Reduceron.

   The GPU would provide large quantities of fully-programmable (if memory-constrained) "compute units", to concurrently process large collections of data.

   1/2?

   • Embed this notice
     alcinnz (alcinnz@floss.social)'s status on Tuesday, 14-Jan-2025 04:45:40 JST alcinnz

     in reply to

     The SPUs were cheap vector processors with 256KiB of internal RAM. The whole point was to fit lots of SPUs in the chip! The communicated between themselves, main RAM, & the coordinator (for PS3, a PowerPC core) via FIFO channels on a token-ring network.

     The Reduceron is a simple stack machine targetting Haskell semantics. Implemented mainly being copying lightly-modified data between independently-addressed RAM banks. Not very powerful, but I've taken care of the power with GPUs & SPUs!

     2/2!

   • Embed this notice
     alcinnz (alcinnz@floss.social)'s status on Tuesday, 14-Jan-2025 10:26:52 JST alcinnz

     in reply to

     What are my goals in designing that graphics workstation architecture: Basically I wanted the most computational power for the lowest transistor-cost. And I *generally* like to design my hypothetical computers to be *different*!

     You'd want enough computational power to calculate every highres pixel onscreen at faster-than-realtime. Which is a lot! Lots of numbers & lots of data!

     The SPUs & GPUs fill that need, the Reduceron is there to coordinate them. And because I like the design!

     3/2!