Ok I think this is done, only thing left to do is fit-check a STEP export against the enclosure before I order the board (see lesson learned above...)
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:19 JST Andrew Zonenberg -
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:06 JST Andrew Zonenberg And a second new line in the PCB checklist: "read errata of every chip in the design"
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:06 JST Andrew Zonenberg Progress! The spaghetti bowl is even larger.
All of this cabling is in use for this test setup. Currently troubleshooting the SPI interface between the supervisor and main MCU.
Once that's done I'll have full connectivity between all of the various subsystems so I can control and monitor health from one spot.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:07 JST Andrew Zonenberg Sooo I guess new line in my pcb checklist: stm32 jtrst pin should be dedicated if you're using jtag mode. Don't use it for anything else
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:07 JST Andrew Zonenberg Confirmed it's a silicon bug.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:08 JST Andrew Zonenberg All hard coded strings as the SPI bus to the FPGA isn't up yet.
But progress!
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:08 JST Andrew Zonenberg Sooo I guess the SPI bus to this thing is going to be write only.
The instant I configure the MISO pin in SPI mode, it no longer is acting as JTRST. And the JTAG interface resets and I lose the ability to program the thing until I manually stick a wire across the RST# pin and release it while racing the firmware and JTAG dongle trying to hold the chip in reset before it reaches the point of enabling the SPI interface.
Good news is, there's nothing to read back from the front panel anyway. The power and reset buttons are raw 3.3V GPIOs and the remainder of the SPI bus is entirely FPGA -> MCU traffic.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:09 JST Andrew Zonenberg Display is alive! The full update cycle takes about 45 seconds (not sure if normal or I'm doing something wrong) so I'll probably need to make it nonblocking to keep the LEDs alive during update cycles.
And so far I just have raw framebuffer pixel write methods and need to add some routines for drawing lines, text, etc to make it useful. But the hardware interface work is mostly done
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:09 JST Andrew Zonenberg Ok checked the datasheet and sure enough it specifies a 21 second typical update time at 25C for an image with no red; images with red are slower.
They apparently sell a "fast update" variant that's 3.8 sec update cycle time and monochrome.
Good to know but not particularly a deal breaker for my use case. It's only going to be used for IP address, version, etc. configuration display and will only update when these change, the system is power cycled, or every 24 hours (manufacturer recommendation to prevent ghosting)
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:09 JST Andrew Zonenberg Time to start doing actual graphics design now.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:10 JST Andrew Zonenberg Ok so the mcu is alive, i updated my peripheral library to (I think) correctly initialize the PLL, and it can toggle some LEDs.
UART isn't working. Might be swapped tx/rx flywires on the test points, bad alt function config, bad baud rate divisor due to incorrect PLL config, or something else. Getting tired and will troubleshoot tomorrow morning.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:10 JST Andrew Zonenberg UART is working, was actually hanging waiting for the internal LDO to initialize (which it already had) because I was polling the status register wrong.
I2C is up, IO expander is working, and I can read the thermal sensor. Next step is getting the e-ink display working but it's almost time for a certain someone to wake up so morning lab time is over.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:11 JST Andrew Zonenberg Hmm, smelling like maybe incomplete reflow. I don't do 0.5mm BGA that often and I had a bad paste print so I added flux and reflowed with no paste.
Pressed a bit on the board and after a power cycle its working fine so maybe marginal solder joint? Will need to investigate.
Either way, the problem of "when FPGA is configred, front panel MCU goes unresponsive over JTAG" persists and will be... fun... to troubleshoot.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:11 JST Andrew Zonenberg Looks like FRONTPANEL_MISO is on PB4 which defaults to NJTRST. And I guess it's floating low.
Adding a pullup FPGA side should fix this.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:12 JST Andrew Zonenberg Front panel board assembled. Eink display isn't secured yet (will be VHB'd eventually) so I can remove it if needed for rework.
The MCU is alive and responsive over JTAG... Until I boot up the FPGA. For some reason OpenOCD then loses contact with it.
Unsure if one of the IOs has an alt mode I don't know about or there's a board issue or both.
First step will be to load some kind of blinky firmware.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:12 JST Andrew Zonenberg Aaand that's not working. According to gdb I'm in the bootloader region. So somehow BOOT0 is showing high? The flash has valid data in it.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:13 JST Andrew Zonenberg When did the XC7K70T get so small?
I'm debating adding a proof-of-concept of my high speed serial capture block to it, although memory depth will be quite limited. The entire chip has only 4.8 Mbits of memory so with two channels and some BRAM used for other stuff, I'll have a max of ~2 Mpts per channel. That's still a fair bit especially since I'll be capturing after the CDR (i.e. I don't need to oversample).
And then I still have to implement CDR trigger functionality at some point.
But before I do any of that, more ngscopeclient driver stuff to do to support the existing feature set. And probably some more gateware work will be needed to support RX sub-rate modes.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:13 JST Andrew Zonenberg Added RX sub-rate mode support, so now I can use 10.3125 or 5 Gbps as the base and divide down by any power of two down to 625 Mbps.
Also, ngscopeclient now has a new "reverse Viridis" color ramp that's flipped around so full-scale maps to purple and ε maps to yellow (the actual zero value maps to transparent as before, so the "no counts" part of a density map is clearly distinguishable from low-probability jitter).
I find this this more pleasing and less harsh on the eyes vs using regular Viridis when looking at at BER plots where most of the plot is a BER of ~0.5 (mapped to yellow).
Next up is adding support for live streaming BER measurements as well as deep integration of BER over long time periods.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:13 JST Andrew Zonenberg Front panel PCB came in while I was in Germany. Back side is assembled and looks good optically but forgot to take a pic of it.
Next step, stuffing the front and seeing if I managed to make 0.5mm BGA work on OSHPark 4L.
If that works, then I can start writing firmware!
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:14 JST Andrew Zonenberg After several hours of debugging, I have the TX logic and CPLL of the GTX resetting under control of my own custom logic (not using the 7 series transceiver wizard black box). Still using their reset FSM for the RX.
And I can dynamically switch between CPLL and QPLL at run time, including sub-rate modes, on the transmitter.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:14 JST Andrew Zonenberg So now all I need to do is make some API changes to libscopehal and update the ngscopeclient GUI accordingly (right now it assumes BERTs have a single global timebase and doesn't support a per-lane timebase configuration).
At which point I should be able to synthesize PRBSes at 10.3125 Gbps divided by 1, 2, 4, 8, or 16, or 5 Gbps divided by 1, 2, 4, or 8 (div 16 would be 312.5 Mbps which is below the 500 Mbps minimum for the GTX).
More options possible if I add support for runtime partial reconfiguration of the CPLL but I can do this much with fixed CPLL and QPLL frequencies, just muxing between the two and configuring sub-rates.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:15 JST Andrew Zonenberg The bench is definitely busy now. But it's closer to the test setup I wanted (short SMA cables going to the big scope and the long 2.92mm cables to the BERT).
Still quite a bit more firmware dev to do, plus eventually reworking those two busted input buffers on channels 2 and 3.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:15 JST Andrew Zonenberg Hooked up my little DS125DF111 based PRBS generator. It doesn't have a very stable clock source and you can clearly see the jitter in the eye pattern and bathtub curve (on channel RX1, bottom plot).
But it can go down to 1.25 Gbps and the ML4039 doesn't go below about 8, so I'll need it for testing sub-rate receive modes.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:16 JST Andrew Zonenberg Looks like a 30mm fan fits comfortably. I probably won't use it at all, but it's nice to have the option if I need it.
Also made a few more final visual improvements to the front/rear panels and moved the power supply board so it fits better around the fan and DC inlet. I'm going to have to custom crimp that extension cable but I think it's the best option for now.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:16 JST Andrew Zonenberg What's better than a BERT? Two of them!
Here's the trigger crossbar BERT module crossed over with my multiLane ML4039-BTP BERT sending PRBS7's at 10.3125 Gbps.
Default settings on equalizers, 42" of Koaxis KF086 cable.
This should be a nice development test setup once I implement things like error injection and deep BER integration on my gateware.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:17 JST Andrew Zonenberg Fixed a few small formatting issues, back to white on the vertical lines. I think it looks better this way plus it'll save the setup fees of a second silkscreen mask.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:17 JST Andrew Zonenberg Decided to add a cooling solution just in case. I *probably* can get away without it but didn't want to risk it.
Unfortunately it looks like the extruded 1U chassis design is just a tad too low to fit a 40mm fan.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:18 JST Andrew Zonenberg Updated chassis renders with model number and some other small layout tweaks.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:18 JST Andrew Zonenberg Redid the whole back panel text and line layout and changed the inter-group lines to black to provide distinction from the operating-voltage markings.
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Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:19 JST Andrew Zonenberg I think this will do nicely.
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