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   iced depresso (icedquinn@blob.cat)'s status on Sunday, 18-Feb-2024 09:00:35 JST iced depresso

   • Lizzie
   @lizzie :neocat_thonk: there might be more memory pressure overall, since they tend to have a lot more instructions and tend to be bigger programs. but i'm told pipelining often undoes the performance issue because they are always the same size, so the hardware is able to shuttle it around and decode it behind the run head or something.
   
   you only pay for registers you move and more registers means more temporaries without touching stack, so a function with 2 inputs and 1 output doesn't really care about the amount of registers in the call frame, since it will just leave the ones it doesn't use alone
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     iced depresso (icedquinn@blob.cat)'s status on Sunday, 18-Feb-2024 09:01:31 JST iced depresso

     in reply to

     • Lizzie
     @lizzie so idk yeah if you use a lot of temporaries you will have to save the registers somewhere, but you were already doing worse on cisc i gess
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     iced depresso (icedquinn@blob.cat)'s status on Sunday, 18-Feb-2024 09:27:02 JST iced depresso

     in reply to

     • Lizzie
     @lizzie it might have been an attempt to give c stack frames their own operator since its such a common idiom
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     Lizzie (lizzie@brain.worm.pink)'s status on Sunday, 18-Feb-2024 09:27:09 JST Lizzie

     in reply to

     @icedquinn wait yeah you only need to save the registers you use. i thought intel had an instruction that just saved the whole set for some reason but im not even sure thats a thing, and if so, risc processors definitely wouldn’t have it. more registers also means you can pass more function args via register so that’s neat