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   Emi Yusa (gnuxeava@mk.absturztau.be)'s status on Thursday, 29-Sep-2022 13:33:47 JST Emi Yusa

   how tf riscv so efficient

   • Embed this notice
     翠星石 (suiseiseki@freesoftwareextremist.com)'s status on Thursday, 29-Sep-2022 13:33:46 JST 翠星石

     in reply to
     @GNUxeava Since a less braindead instruction set without as much cruft on a microprocessor constructed on a modern node doesn't waste power on cruft?
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     翠星石 (suiseiseki@freesoftwareextremist.com)'s status on Thursday, 29-Sep-2022 16:58:49 JST 翠星石

     in reply to

     • Iska :emacs_thinking:​
     @iska I'm pretty sure the provided MIPS designs are proprietary, so them being royalty-free wouldn't fix the problem.
     I'm pretty sure the patents on the base MIPS instruction set, plus a number of extensions should have all expired by now - so you can indeed re-implement the base MIPS instruction set plus some extensions without having to pay royalties.
     
     The example RISC-V hardware designs are under a license that results in the design being a free hardware design.
     Sure the design is royalty-free also, but that's really an irrelevant thing.
     
     As for currently produced RISC-V designs that end up being fabbed, they're all ultra-proprietary and have patents up the wazoo.
   • Embed this notice
     Iska :emacs_thinking:​ (iska@mstdn.starnix.network)'s status on Thursday, 29-Sep-2022 16:58:50 JST Iska :emacs_thinking:​

     in reply to

     • 翠星石

     @Suiseiseki @GNUxeava

     less braindead ISA

     It's literally MIPS but royalty-free aaaa