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to implement the SPI analyzer, I decided to clock the FPGA logic from the SPI clock directly instead of using the FPGA system clock (48 MHz), which would otherwise allow sampling SPI signals at up to 24 MHz; many real-world uses of SPI are above that (e.g. this SD card was clocked at 27 MHz, ECP5 configures at 65 MHz)

the FPGA logic runs at about 120 MHz, but since nextpnr doesn't support constraining input delays, you'll most likely start having issues somewhere below that frequency