Embed Notice

@aleksorsist @urja My vision a while back was a series of series of edge detectors feeding into serial/parallel pattern matching blocks, then a state machine acting on the output.

So you could have it look for "falling edge on CH1" then "0x41 serially on CH2 data clocked by CH3 rising edge" then "0x20 serially on same pins", with a rising edge on CH1 or a mismatch of either byte clearing the state machine back to the start.

This would give you a SPI pattern match. I'm sure you can see the potential to implement I2C etc. on the same logic block.