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<blockquote style="position: relative; padding-left: 55px;"><section><a href="https://mastodon.social/users/whitequark/statuses/114431438511662148">✧✦Catherine✦✧ (whitequark@mastodon.social)'s status on Thursday, 01-May-2025 16:39:44 JST</a><a href="https://mastodon.social/@whitequark" title="whitequark@mastodon.social"><img src="https://gnusocial.jp/avatar/105710-48-20230309163231.webp" width="48" height="48" alt="✧✦Catherine✦✧" style="position: absolute; left: 0; top: 0;">✧✦Catherine✦✧</a><div><a href="https://mastodon.social/@whitequark/114425593164979916" rel="in-reply-to">in reply to</a></div></section><article><p>my collection of upsetting facts grows</p></article><footer><a rel="bookmark" href="https://gnusocial.jp/conversation/4978439#notice-9767000">In conversation</a><time datetime="2025-05-01T16:39:44+09:00" title="Thursday, 01-May-2025 16:39:44 JST">about 3 days ago</time> <span>from <span><a href="https://mastodon.social/@whitequark/114431438511662148" rel="external" title="Sent from mastodon.social via ActivityPub">mastodon.social</a></span></span><a href="https://mastodon.social/@whitequark/114431438511662148">permalink</a><h4>Attachments</h4><ol><li><label><a rel="external" href="https://gnusocial.jp/attachment/4553548"># Things you wish ARM told you about this core; more explicitly or at all:
#  * The bit order in the scan chain 1 is backwards. This is technically documented (read p. 5-34)
#    _very carefully_, but not in a way that anybody would notice.
#  * The bit order in the data field of the scan chain 2 is documented backwards, but is not.
#  * If you interrupt the core with DBGREQ, you have to drop DBGREQ before it'll do anything.
#  * DBGACK can be set without DBGREQ. It is because DBGACK does a double duty as the signal that
#    causes the peripherals to ignore side effectful memory accesses while debugging. They tell you
#    to make your debugger set it while performing memory accesses.
#  * ... except that you do want peripherals to be manipulatable by your debugger, so sometimes
#    you don't actually want to do that. Also goddess knows whether any given peripheral does
#    anything different with DBGACK asserted and if yes then what the semantics of it is.
#  * The documentation says you can set bit 33 (DBGBREAK) on loads/stores. This is false. You have
#    to set it on the preceding instruction (usually a nop). It does technically say that DBGBREAK
#    is pipeline on top of page 5-41 but in a very confusing way.
#  * Be careful when running `LDR R0, [R0]`. Since you are putting data on the data bus, and not
#    directly into the register, the address in R0 still influences the result: if it's unaligned,
#    the data will be transposed bytewise.</a></label><br><a href="https://files.mastodon.social/media_attachments/files/114/431/437/801/187/276/original/66fcd24fbd7b537b.png" rel="external">https://files.mastodon.social/media_attachments/files/114/431/437/801/187/276/original/66fcd24fbd7b537b.png</a></li></ol></footer></blockquote>

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✧✦Catherine✦✧ (whitequark@mastodon.social)'s status on Thursday, 01-May-2025 16:39:44 JST ✧✦Catherine✦✧
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my collection of upsetting facts grows
In conversationabout 3 days ago from mastodon.socialpermalink
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1. # Things you wish ARM told you about this core; more explicitly or at all: # * The bit order in the scan chain 1 is backwards. This is technically documented (read p. 5-34) # _very carefully_, but not in a way that anybody would notice. # * The bit order in the data field of the scan chain 2 is documented backwards, but is not. # * If you interrupt the core with DBGREQ, you have to drop DBGREQ before it'll do anything. # * DBGACK can be set without DBGREQ. It is because DBGACK does a double duty as the signal that # causes the peripherals to ignore side effectful memory accesses while debugging. They tell you # to make your debugger set it while performing memory accesses. # * ... except that you do want peripherals to be manipulatable by your debugger, so sometimes # you don't actually want to do that. Also goddess knows whether any given peripheral does # anything different with DBGACK asserted and if yes then what the semantics of it is. # * The documentation says you can set bit 33 (DBGBREAK) on loads/stores. This is false. You have # to set it on the preceding instruction (usually a nop). It does technically say that DBGBREAK # is pipeline on top of page 5-41 but in a very confusing way. # * Be careful when running `LDR R0, [R0]`. Since you are putting data on the data bus, and not # directly into the register, the address in R0 still influences the result: if it's unaligned, # the data will be transposed bytewise.
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