P.S. I haven't stated what endianness I'd use for the underlying CPU for this interpreter. It'd be nice if there were (a bit of) a Control/Status Register (CSR) allowing me to configure this! Shouldn't complicate the circuitry much...
P.S. I haven't stated what endianness I'd use for the underlying CPU for this interpreter. It'd be nice if there were (a bit of) a Control/Status Register (CSR) allowing me to configure this! Shouldn't complicate the circuitry much...
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