The G5 CPU can't run in little-endian mode. It may be the only PowerPC CPU that isn't bi-endian. Apple didn't need little-endian support but they did need some other obscure compatibility features not found in other PowerPC chips (there's a "zero a cache line" opcode that Mac code expected to zero a certain # of bytes, so G5's emulate zeroing that # of bytes, which is now smaller than a cache line, which other PowerPC's don't, a compatibility feature only needed to run 32-bit Mac PowerPC code).