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    Jure Repinc :linux: :kde: (jrepin@mstdn.io)'s status on Monday, 11-Nov-2024 18:49:29 JSTJure Repinc :linux: :kde:Jure Repinc :linux: :kde:

    RISC-V Vector Extension overview
    🔗 http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html

    "The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
    […]
    The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."

    #RISCV #RISC_V #RVV #ComputerArchitecture #ISA #InstructionSetArchitecture #CPU #CPUs #processor #processors

    In conversationMonday, 11-Nov-2024 18:49:29 JST from mstdn.iopermalink

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      RISC-V Vector Extension overview
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