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<blockquote style="position: relative; padding-left: 55px;"><section><a href="https://mstdn.social/users/DM_Ronin/statuses/113452463003083026">ilias :thepiratebay: (dm_ronin@mstdn.social)'s status on Saturday, 09-Nov-2024 20:14:06 JST</a><a href="https://mstdn.social/@DM_Ronin" title="dm_ronin@mstdn.social"><img src="https://gnusocial.jp/avatar/103688-48-20241109124245.webp" width="48" height="48" alt="ilias :thepiratebay:" style="position: absolute; left: 0; top: 0;">ilias :thepiratebay:</a></section><article><p>TIL about BDSM</p><p>A BDSM register</p><p><a href="https://mstdn.social/tags/Embedded" rel="tag">#Embedded</a> <a href="https://mstdn.social/tags/Intel" rel="tag">#Intel</a> <a href="https://mstdn.social/tags/Hardware" rel="tag">#Hardware</a> <a href="https://mstdn.social/tags/Processor" rel="tag">#Processor</a> <a href="https://mstdn.social/tags/CPU" rel="tag">#CPU</a> <a href="https://mstdn.social/tags/Tech" rel="tag">#Tech</a> <a href="https://mstdn.social/tags/Technology" rel="tag">#Technology</a></p></article><footer><a rel="bookmark" href="https://gnusocial.jp/conversation/3968342#notice-7752180">In conversation</a><time datetime="2024-11-09T20:14:06+09:00" title="Saturday, 09-Nov-2024 20:14:06 JST">about 16 days ago</time> <span>from <span><a href="https://mstdn.social/@DM_Ronin/113452463003083026" rel="external" title="Sent from mstdn.social via ActivityPub">mstdn.social</a></span></span><a href="https://mstdn.social/@DM_Ronin/113452463003083026">permalink</a><h4>Attachments</h4><ol><li><label><a rel="external" href="https://gnusocial.jp/attachment/3448124">Base Data of Stolen Memory (BDSM_0_0_0_PCI) – Offset B0This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BC bits 31:20).Bit Range: 31:20
Default: 0x0
Access: RW/L
Field Name and Description: (BDSM) This register contains bits 31 to 20 of the base address of stolen DRAM memory. BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size (PCI Device 0 offset 50 bits 15:8) from TOLUD (PCI Device 0 offset BC bits 31:20).Bit Range: 19:1
Default: 0h
Access: RO
Field Name and Description: ReservedBit Range: 0
Default: 0x0
Access: RW/L
Field Name and Description: 
(LOCK)
This bit will lock all writable settings in this register, including itself.</a></label><br><a href="https://media.mstdn.social/media_attachments/files/113/452/453/524/853/207/original/4c8dad4d186957da.png" rel="external">https://media.mstdn.social/media_attachments/files/113/452/453/524/853/207/original/4c8dad4d186957da.png</a></li></ol></footer></blockquote>

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ilias :thepiratebay: (dm_ronin@mstdn.social)'s status on Saturday, 09-Nov-2024 20:14:06 JST ilias :thepiratebay:
TIL about BDSM
A BDSM register
#Embedded #Intel #Hardware #Processor #CPU #Tech #Technology
In conversationabout 16 days ago from mstdn.socialpermalink
Attachments
1. Base Data of Stolen Memory (BDSM_0_0_0_PCI) – Offset B0 This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BC bits 31:20). Bit Range: 31:20 Default: 0x0 Access: RW/L Field Name and Description: (BDSM) This register contains bits 31 to 20 of the base address of stolen DRAM memory. BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size (PCI Device 0 offset 50 bits 15:8) from TOLUD (PCI Device 0 offset BC bits 31:20). Bit Range: 19:1 Default: 0h Access: RO Field Name and Description: Reserved Bit Range: 0 Default: 0x0 Access: RW/L Field Name and Description: (LOCK) This bit will lock all writable settings in this register, including itself.
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