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    Andrew Zonenberg (azonenberg@ioc.exchange)'s status on Wednesday, 27-Mar-2024 03:35:55 JSTAndrew ZonenbergAndrew Zonenberg

    Anyway, good progress. I think I'll start building out the RX-side pattern checker logic in the FPGA and get scopehal integration for the RX channels up, including sub-rate mode and display of these (buggy) eye patterns.

    Hopefully by the time I get that done I'll have an answer from Xilinx support that might push me in the right direction...

    In conversationabout 7 months ago from ioc.exchangepermalink
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